MC68HC11E0MFNE2 Freescale Semiconductor, MC68HC11E0MFNE2 Datasheet - Page 197
MC68HC11E0MFNE2
Manufacturer Part Number
MC68HC11E0MFNE2
Description
MCU 8-BIT 512 RAM 2MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC11E0MFNE2
Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
52-PLCC
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Package
52PLCC
Family Name
HC11
Maximum Speed
2 MHz
Operating Supply Voltage
3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC11E0MFNE2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Figure 2
a 2-MHz E-clock rate) and the alternate baud rate (1200 baud at a 2-MHz E-clock rate). The host
computer sends an initial $FF character, which is used by the bootloader to determine the baud rate that
will be used for the downloading operation. The top half of
Receive data samples at [1] detect the falling edge of the start bit and then verify the start bit by taking a
sample at the center of the start bit time. Samples are then taken at the middle of each bit time [2] to
reconstruct the value of the received character (all 1s in this case). A sample is then taken at the middle
of the stop bit time as a framing check (a 1 is expected) [3]. Unless another character immediately follows
this $FF character, the receive data line will idle in the high state as shown at [4].
The bottom half of
from the host at 1200 baud. Because the receiver is set to 7812 baud, the receive data samples are taken
at the same times as in the upper half of
the start bit at 7812 baud [6].
Freescale Semiconductor
NOTE: Software can change some aspects of the memory map after reset.
$BFC0
$01FF
$BFFF
$FFC0
$0000
$B7FF
$FFFF
$103F
$B600
$BF00
$D000
$1000
shows how the bootloader program differentiates between the default baud rate (7812 baud at
MODA = 0
MODB = 1
SINGLE
CHIP
Figure 2
Figure 1. MC68HC711E9 Composite Memory Map
MULTIPLEXED
EXTERNAL
EXTERNAL
EXTERNAL
EXPANDED
MODA = 1
MODB = 1
shows how the receiver will incorrectly receive the $FF character that is sent
M68HC11 Bootstrap Mode, Rev. 1.1
BOOTSTRAP
MODA = 0
MODB = 0
SPECIAL
Figure
2. The start bit at 1200 baud [5] is 6.5 times as long as
EXTERNAL
EXTERNAL
EXTERNAL
MODA = 1
MODB = 0
SPECIAL
TEST
Figure 2
shows normal reception of $FF.
Automatic Selection of Baud Rate
REGISTER
12K USER
512-BYTE
512-BYTE
EEPROM
64-BYTE
(or OTP)
EPROM
BLOCK
BOOT
ROM
RAM
(MAY BE REMAPPED
TO ANY 4K BOUNDARY)
(MAY BE REMAPPED
TO ANY 4K BOUNDARY)
(MAY BE DISABLED
BY AN EEPROM BIT)
(MAY BE DISABLED
BY AN EEPROM BIT)
VECTORS
VECTORS
SPECIAL
NORMAL
$BFC0
MODE
$FFC0
MODE
$BFFF
$FFFF
197
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