DF2117VT20V Renesas Electronics America, DF2117VT20V Datasheet - Page 122

• Manufacturer Part Number: DF2117VT20V
• Description: MCU 16BIT FLASH 3V 160K 144-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2117VT20V

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: FIFO, I²C, LPC, SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 112
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 4.1 shows an example of the reset sequence.
4.3.2
If an interrupt is accepted immediately after a reset and before the stack pointer (SP) is initialized,
the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all
interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction
of a program is always executed immediately after a reset, make sure that this instruction
initializes the SP (example: MOV.L #xx: 32, SP).
4.3.3
After a reset is cancelled, the module stop control registers (MSTPCRH, MSTPCRL, MSTPCRA,
MSTPCRB) are initialized, and all modules except the DTC operate in module stop mode.
Therefore, the registers of on-chip peripheral modules cannot be read from or written to. To read
from and write to these registers, clear module stop mode. For details on module stop mode, see
section 26, Power-Down Modes.
Rev. 2.00 Sep. 28, 2009 Page 80 of 994
REJ09B0452-0200
Interrupts Immediately after Reset
On-Chip Peripheral Modules after Reset is Cancelled
(1) Reset exception handling vector address (1) U = H'000000 (1) L = H'000002
(2) Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2)U + (2)L)
(4) First program instruction
φ
RES
Internal address bus
Internal read signal
Internal write signal
Internal data bus
Figure 4.1 Reset Sequence (Mode 2)
(1) U
(2)
Vector
fetch
U
High
(2)
(1) L
L
processing
Internal
program instruction
Prefetch of first
(3)
(4)