MC68HC16Z1CEH16 Freescale Semiconductor, MC68HC16Z1CEH16 Datasheet - Page 4

• Manufacturer Part Number: MC68HC16Z1CEH16
• Description: IC MCU 16BIT 16MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH16

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Processor Series: HC16Z
• Core: CPU16
• Data Bus Width: 16 bit
• Controller Family/series: 68HC16
• No. Of I/o's: 26
• Ram Memory Size: 1KB
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MOTOROLA
Num
(V
NOTES:
1
2
3
4
5
6
DD
1. Tested with a 32.768 kHz reference.
2. All internal registers retain data at 0 Hz.
3. Assumes that stable V
4. Internal VCO frequency (f
5. This parameter is periodically sampled rather than 100% tested.
6. Assumes that a low-leakage external filter network is used to condition clock synthesizer in-
7. Proper layout procedures must be followed to achieve specifications.
8. Jitter is the average deviation from the programmed frequency measured over the specified
measured from the time V
tion also applies to the period required for PLL lock after changing the W and Y frequency
control bits in the synthesizer control register (SYNCR) while the PLL is running, and to the
period required for the clock to lock after LPSTOP.
The SYNCR X bit controls a divide-by-two circuit that is not in the synthesizer feedback loop.
put voltage. Total external resistance from the XFC pin due to external leakage must be
greater than 15 M
pending upon operating environment.
interval at maximum f
plies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via
V
for a given interval. When jitter is a critical constraint on control system operation, this param-
eter should be measured during functional testing of the final system.
PLL Reference Frequency Range
System Frequency
PLL Lock Time
VCO Frequency
Limp Mode Clock Frequency
CLKOUT Jitter
and V
DDSYN
When X = 0, the divider is enabled, and f
When X = 1, the divider is disabled, and f
X must equal one when operating at maximum specified f
On-Chip PLL System Frequency
External Clock Operation
SYNCR X bit = 0
SYNCR X bit = 1
Short term (5 s interval)
Long term (500 s interval)
DDSYN
and V
Characteristic
5,6,7,8
= 5.0 Vdc
3,5,6,7
SS
4
Freescale Semiconductor, Inc.
2
and variation in crystal oscillator frequency increase the J
For More Information On This Product,
sys
Table A–4 Clock Control Timing
to guarantee this specification. Filter network geometry can vary de-
DDSYN
. Measurements are made with the device powered by filtered sup-
VCO
DD
5%, V
and V
) is determined by SYNCR W and Y bit values.
Go to: www.freescale.com
is applied, and that the crystal oscillator is stable
SS
DDSYN
= 0 Vdc, T
sys
sys
are valid until RESET is released. This specifica-
Symbol
= f
= f
f
f
f
VCO
J
t
limp
f
sys
lpll
VCO
ref
clk
VCO
A
= T
L
4.
2.
to T
Minimum
sys
0.131
H
–1.0
–0.5
.
25
dc
dc
—
—
—
—
, Stable External Reference )
2 (f
f
Maximum
sys
f
sys
25.17
25.17
25.17
sys
1.0
0.5
50
20
max /2
clk
max
.
max)
Lock time is
percentage
M68HC16ZEC25/D
MHz
MHz
MHz
Unit
kHz
ms
%
1
4