DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 359
DF36034GFPJ
Manufacturer Part Number
DF36034GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36034GFPJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36034GFPJ
HD64F36034GFPJ
HD64F36034GFPJ
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15.5.2
The bit rate and bit timing are set by the bit configuration register (BCR). The CAN controllers
connected to the CAN bus should be set so that all of them have the same baud rate and same bit
width. One bit time consists of total settable Time Quantum (TQ).
The SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus.
Normal bit edge changes in this segment. The PRSEG is a segment for adjusting the physical
delay between networks. The PHSEG1 is a buffer segment for adjusting positive phase drift. This
segment is extended when re-synchronization is established. The PHSEG2 is a buffer segment for
adjusting negative phase drift. This segment is shortened when re-synchronization is established.
The range of settable values in BCR (TSG1, TSG2, BRP, and SJW) is shown in table 15.2.
Table 15.2 Settable Values in BCR
Notes: 1. The time quanta values for the TSEG1 and TSEG2 are as follows: TSG value
Name
Time segment 1
Time segment 2
Baud rate prescaler
Re-Synchronization Jump width
2. In the CAN specifications, the Re-Synchronization Jump Width is stipulated as
3. The minimum value of TSG1 is stipulated in the CAN specifications:
4. The minimum value of TSG2 is stipulated in the CAN specifications:
Bit Timing
4
SJW0 to SJW1 in BCR.
TSG1 > TSG2
TSG2
SJW
SJW
1 time quantum
1. The value of SJW is given by adding 1 to the setting value of the bits
SYNC_SEG
Figure 15.5 CAN Bit Configuration
Abbreviation
TSG1*
TSG2*
BRP
SJW*
1 bit time (8 to 25 time quanta)
PRSEG
Time segment 1 (TSG1)
4 to 16 time quanta
2
1
1
Section 15 Controller Area Network for Tiny (TinyCAN)
PHSEG1
Sampling point
Min. Value
3*
1*
1
0
3
4
Rev. 4.00 Mar. 15, 2006 Page 325 of 556
2 to 8 time quanta
Time segment 2
PHSEG2
(TSG2)
Max. Value
15
7
63
3
REJ09B0026-0400
1
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