MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 124

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5
5.10.2.8 Recommended BDM Connection
5.10.3 Deterministic Opcode Tracking
5-24
STATUS CONTROL BIT
S/C
16
Command and data transfers initiated by the development system should clear bit 16.
The current implementation ignores this bit; however, Freescale reserves the right to
use this bit for future enhancements.
In order to provide for use of development tools when an MCU is installed in a system,
Freescale recommends that appropriate signal lines be routed to a male Berg connec-
tor or double-row header installed on the circuit board with the MCU, as shown in the
following figure.
CPU32 function code outputs are augmented by two supplementary signals to monitor
the instruction pipeline. The instruction pipe (IPIPE) output indicates the start of each
new instruction and each mid-instruction pipeline advance. The instruction fetch
15
Table 5-6 CPU Generated Message Encoding
Bit 16
0
0
1
1
1
Freescale Semiconductor, Inc.
Figure 5-11 BDM Connector Pinout
For More Information On This Product,
Figure 5-10 BDM Serial Data Word
FFFF
FFFF
0000
0001
Data
xxxx
CENTRAL PROCESSING UNIT
RESET
GND
GND
V
Go to: www.freescale.com
DD
DS
Valid Data Transfer
Command Complete; Status OK
Not Ready with Response; Come Again
BERR Terminated Bus Cycle; Data Invalid
Illegal Command
1
3
5
7
9
10
2
4
6
8
DATA FIELD
BERR
BKPT/DSCLK
FREEZE
IFETCH/DSI
IPIPE/DSO
Message Type
32 BERG
USER’S MANUAL
MC68331
0