MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 59
![IC MCU 32BIT 20MHZ 132-PQFP](/photos/39/60/396098/4243113_sml.jpg)
MC68331CEH20
Manufacturer Part Number
MC68331CEH20
Description
IC MCU 32BIT 20MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68331CEH20
Core Processor
CPU32
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
18
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Controller Family/series
68K
No. Of I/o's
18
Cpu Speed
20MHz
No. Of Timers
1
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
2
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Data Ram Size
80 B
Interface Type
QSPI, SCI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
20MHz
Program Memory Size
Not Required
Total Internal Ram Size
80Byte
# I/os (max)
18
Number Of Timers - General Purpose
1
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68331CEH20
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68331CEH20
Manufacturer:
FREESCLA
Quantity:
20 000
MSTR — Master/Slave Mode Select
WOMQ — Wired-OR Mode for QSPI Pins
BITS — Bits Per Transfer
CPOL — Clock Polarity
CPHA — Clock Phase
MC68331TS/D
MSTR configures the QSPI for either master or slave mode operation. This bit is cleared on reset and
may only be written by the CPU.
WOMQ allows the wired-OR function to be used on QSPI pins, regardless of whether they are used as
general-purpose outputs or as QSPI outputs. WOMQ affects the QSPI pins regardless of whether the
QSPI is enabled or disabled.
In master mode, when BITSE in a command is set, the BITS field determines the number of data bits
transferred. When BITSE is cleared, eight bits are transferred. Reserved values default to eight bits.
BITSE is not used in slave mode.
The following table shows the number of bits per transfer.
CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to
produce a desired clock/data relationship between master and slave devices.
CPHA determines which edge of SCK causes data to change and which edge causes data to be cap-
tured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave
devices. CPHA is set at reset.
0 = QSPI is a slave device and only responds to externally generated serial data.
1 = QSPI is system master and can initiate transmission to external SPI devices.
0 = Outputs have normal MOS drivers.
1 = Pins designated for output by DDRQS have open-drain drivers.
0 = The inactive state value of SCK is logic level zero.
1 = The inactive state value of SCK is logic level one.
0 = Data is captured on the leading edge of SCK and changed on the following edge of SCK.
1 = Data is changed on the leading edge of SCK and captured on the following edge of SCK.
Freescale Semiconductor, Inc.
For More Information On This Product,
BITS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Go to: www.freescale.com
Bits per Transfer
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
16
10
11
12
13
14
15
8
9
59