MC68HC711E9CFNE3 Freescale Semiconductor, MC68HC711E9CFNE3 Datasheet - Page 170

• Manufacturer Part Number: MC68HC711E9CFNE3
• Description: IC MCU 3MHZ 12K OPT 52-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Peripheral Interface (SPI)
8.6.1 Master In/Slave Out
8.6.2 Master Out/Slave In
8.6.3 Serial Clock
8.6.4 Slave Select
Technical Data
170
MISO is one of two unidirectional serial data signals. It is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device is
not selected.
The MOSI line is the second of the two unidirectional serial data signals.
It is an output from a master device and an input to a slave device. The
master device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data.
SCK, an input to a slave device, is generated by the master device and
synchronizes data movement in and out of the device through the MOSI
and MISO lines. Master and slave devices are capable of exchanging a
byte of information during a sequence of eight clock cycles.
Four possible timing relationships can be chosen by using control bits
CPOL and CPHA in the serial peripheral control register (SPCR). Both
master and slave devices must operate with the same timing. The SPI
clock rate select bits, SPR[1:0], in the SPCR of the master device, select
the clock rate. In a slave device, SPR[1:0] have no effect on the
operation of the SPI.
The slave select (SS) input of a slave device must be externally asserted
before a master device can exchange data with the slave device. SS
must be low before data transactions and must stay low for the duration
of the transaction.
The SS line of the master must be held high. If it goes low, a mode fault
error flag (MODF) is set in the serial peripheral status register (SPSR).
To disable the mode fault circuit, write a 1 in bit 5 of the port D data
Serial Peripheral Interface (SPI)
M68HC11E Family — Rev. 3.2
MOTOROLA