DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 150

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
3. This chip has a break function to implement on-board emulation for specific customers. To use
Incorrect NMI Operation Factors: Abnormal Interrupts Input to the Chip Pins
If an abnormal interrupt which was not specified in the electrical characteristics is input to a pin
during a chip operation, the chip may be destroyed. In this case, the operation of the chip will not
be guaranteed.
When an abnormal interrupt has been input to a pin, the chip may not be destroyed; however, the
internal circuits of the chip may partially or wholly malfunction, and the CPU may enter an
unimagined undefined state when the CPU was designed. If this occurs, it will be impossible to
control the operation of the chip by external pins other than the external reset and standby pins,
and the operation of the NMI will not be guaranteed. In this case, after some specified signals have
been input to the pins, input an external reset so that the chip can enter the normal program
execution state again.
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REJ09B0325-0300
this break function, execute the BRK instruction (H'5770). Note that the BRK instruction is
usually undefined. Therefore, if the CPU accidentally executes the instruction, the chip will
perform exceptional processing and will enter the break mode. In the break mode, interrupts
including the NMI are inhibited and the count of the watch dog timer will be stopped. Then by
executing the RTB (H'56F0) instruction, the break mode will be cancelled, and usual program
execution will resume. When the execution is reset during break mode, the CPU enters the
reset state and the break mode is cancelled. Once the reset has been cancelled, normal program
execution will resume after the reset exception processing has been executed.