DF2148BFA20 Renesas Electronics America, DF2148BFA20 Datasheet - Page 603
![IC H8S MCU FLASH 128K 100-QFP](/photos/12/21/122166/qfp100-g1_pkg_sml.jpg)
DF2148BFA20
Manufacturer Part Number
DF2148BFA20
Description
IC H8S MCU FLASH 128K 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of DF2148BFA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SCI, X-Bus
Peripherals
PWM, WDT
Number Of I /o
74
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2148BFA20
HD64F2148BFA20
HD64F2148BFA20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2148BFA20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF2148BFA20IV
Manufacturer:
VISHAY
Quantity:
8 001
Company:
Part Number:
DF2148BFA20IV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF2148BFA20V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2148BFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 603 of 847
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Note:
Bit
0
Bit
7
6
5
4
3
2
STR2
Bit Name Initial Value Slave Host Description
OBF1
Bit Name Initial Value Slave Host Description
DBU27
DBU26
DBU25
DBU24
C/D2
DBU22
* Only 0 can be written to clear the flag.
0
0
0
0
0
0
0
R/(W) * R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R
R
R
R
R
Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. Cleared to 0 when the host processor reads
ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Defined by User
The user can use these bits as necessary.
Command/Data
When the host processor writes to an IDR register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
Defined by User
The user can use this bit as necessary.
Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 547 of 788
REJ09B0300-0300
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