MCF5282CVF66J Freescale Semiconductor, MCF5282CVF66J Datasheet - Page 48
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MCF5282CVF66J
Manufacturer Part Number
MCF5282CVF66J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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ColdFire Core
instruction, fetches the required operands and then executes the required function. Because the IFP and
OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch
instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for
instructions.
The V2 ColdFire core pipeline stages include the following:
When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the operand
execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetched instruction in the
IB until it is required by the OEP.
For register-to-register and register-to-memory store operations, the instruction passes through both OEP
stages once. For memory-to-register and read-modify-write memory operations, an instruction is
effectively staged through the OEP twice: the first time to calculate the effective address and initiate the
operand fetch on the processor’s local bus, and the second time to complete the operand reference and
perform the required function defined by the instruction.
The resulting pipeline and local bus structure allow the V2 ColdFire core to deliver sustained high
performance across a variety of demanding embedded applications.
2.2
The following sections describe the processor registers in the user and supervisor programming models.
The programming model is selected based on the processor privilege level (user mode or supervisor mode)
as defined by the S bit of the status register (SR).
The user-programming model consists of the following registers:
2-2
•
•
•
•
•
•
Two-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage)
— Instruction address generation (IAG) — Calculates the next prefetch address
— Instruction fetch cycle (IC)—Initiates prefetch on the processor’s local bus
— Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO
Two-stage operand execution pipeline (OEP)
— Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the
— Address generation/execute cycle (AGEX)—Calculates operand address or executes the
16 general-purpose 32-bit registers (D0–D7, A0–A7)
32-bit program counter (PC)
8-bit condition code register (CCR)
EMAC registers
— Four 48-bit accumulator registers partitioned as follows:
Memory Map/Register Description
queue
required components for effective address calculation, or the operand fetch cycle
instruction
– Four 32-bit accumulators (ACC0–ACC3)
– Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two
32-bit values for load and store operations (ACCEXT01 and ACCEXT23).
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
(described fully in
Chapter 3, “Enhanced Multiply-Accumulate Unit (EMAC
Table 2-1
lists the processor registers.
Freescale Semiconductor
:
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