DF2367VF33V Renesas Electronics America, DF2367VF33V Datasheet - Page 215
DF2367VF33V
Manufacturer Part Number
DF2367VF33V
Description
IC H8S/2367 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2368VTE34V.pdf
(1044 pages)
Specifications of DF2367VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
DF2367VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2.2.57 (2)
SHAL (SHift Arithmetic Left)
Operation
Rd (left arithmetic shift)
Assembly-Language Format
SHAL.B #2, Rd
Operand Size
Byte
Description
This instruction shifts the bits in an 8-bit register Rd (destination operand) two bits to the left. Bit
6 shifts into the carry flag. Bits 0 and 1 are cleared to 0.
Available Registers
Rd: R0L to R7L, R0H to R7H
Operand Format and Number of States Required for Execution
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
Register direct
Addressing
Mode
SHAL (B)
Mnemonic
SHAL.B
C
Rd
MSB
Operands
b7
#2, Rd
b6
. . . . . .
1st byte
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Receives the previous value in bit 6.
2nd byte
C
Instruction Format
cleared to 0.
cleared to 0.
cleared to 0.
Rev. 4.00 Feb 24, 2006 page 199 of 322
—
I
rd
UI H
—
b1
0
Section 2 Instruction Descriptions
—
3rd byte
LSB
b0
0
—
U
N
0
4th byte
REJ09B0139-0400
Shift Arithmetic
Z
V
States
No. of
C
1
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