HD6473937W Renesas Electronics America, HD6473937W Datasheet - Page 275
HD6473937W
Manufacturer Part Number
HD6473937W
Description
MCU FLASH OTP 60K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheet
1.HD6473937RXV.pdf
(523 pages)
Specifications of HD6473937W
Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
59
Program Memory Size
60KB (60K x 8)
Program Memory Type
OTP
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Part Number:
HD6473937W
Manufacturer:
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Quantity:
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Bit 5: Parity enable (PE)
Bit 5 selects whether a parity bit is to be added during transmission and checked during reception
in asynchronous mode. In synchronous mode parity bit addition and checking is not performed,
irrespective of the bit 5 setting.
Bit 5
PE
0
1
Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit
Bit 4: Parity mode (PM)
Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit
setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and
checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity
bit addition and checking is disabled.
Bit 4
PM
0
1
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total
2. For the case where 5-bit data is selected, see table 10-11.
2. When odd parity is selected, a parity bit is added in transmission so that the total
data before it is sent, and the received parity bit is checked against the parity
designated by bit PM.
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,
a check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an even number.
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a
check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an odd number.
Description
Parity bit addition and checking disabled*
Parity bit addition and checking enabled*
Description
Even parity*
Odd parity*
2
1
1/
2
*
2
(initial value)
(initial value)
261
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