M30624FGAFP#U3 Renesas Electronics America, M30624FGAFP#U3 Datasheet - Page 85

• Manufacturer Part Number: M30624FGAFP#U3
• Description: IC M16C MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30624FGAFP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

[ Description Example ]
DIV
[ Syntax ]
[ Operation ]
[ Function ]
[ Selectable src ]
[ Flag Change ]
[ Related Instructions ]
Chapter 3
Change
R0L/R0
A0/A0
dsp:8[A0]
dsp:16[A0] dsp:16[A1]
dsp:20[A0] dsp:20[A1]
R2R0
Conditions
DIV.size
If the size specifier (.size) is (.B)
If the size specifier (.size) is (.W)
Flag
• This instruction divides R2R0 (R0)
• If src is an A0 or A1 when the size specifier (.size) you selected is (.B), operation is performed on the
• If you specify (.B) for the size specifier (.size), the O flag is set when the operation resulted in the
• If you specify (.W) for the size specifier (.size), the O flag is set when the operation resulted in the
O :
DIV.B
DIV.B
DIV.W
mainder in R2 (R0H)
registers that are operated on when you selected (.B) for the size specifier (.size).
8 low-order bits of A0 or A1.
quotient exceeding 8 bits or the divisor is 0. At this time, R0L and R0H are indeterminate.
quotient exceeding 16 bits or the divisor is 0. At this time, R0 and R2 are indeterminate.
U
R0L (quotient), R0H (remainder)
R0 (quotient), R2 (remainder)
The flag is set when the operation resulted in the quotient exceeding 16 bits (.W) or 8 bits (.B) or
the divisor is 0; otherwise cleared.
R0H/R1
A1/A1
dsp:8[A1]
R3R1
I
Functions
src
A0
#4
R0
O
B
src
*1
S
R1L/R2
[A0]
dsp:8[SB]
dsp:16[SB]
abs20
A1A0
. The remainder has the same sign as the dividend. Shown in ( )
DIVU,DIVX,MUL,MULU
Z
D
*1
C
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
R2R0
by signed src and stores the quotient in R0 (R0L)
B , W
R0
Signed divide
DIVide
src
src
67
;A0’s 8 low-order bits is the divisor.
[ Instruction Code/Number of Cycles ]
3.2 Functions
*1
and the re-
Page= 172
*1
DIV
are the