M30835FJGP#U5 Renesas Electronics America, M30835FJGP#U5 Datasheet - Page 61

IC M32C/83 MCU FLASH 144LQFP

M30835FJGP#U5

Manufacturer Part Number
M30835FJGP#U5
Description
IC M32C/83 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets

Specifications of M30835FJGP#U5

Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
121
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 34x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
144-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30835FJGP#U5M30835FJGP
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Company:
Part Number:
M30835FJGP#U5M30835FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30835FJGP#U5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R
R
M
e
E
3
. v
J
Figure 5.5 V
2
0
C
1
3
4 .
B
8 /
0
1
MAi
DB
BCLK
RAS
CASL
CASH
DW
3
Memory Expansion Mode and Microprocessor Mode
(When accessing the DRAM area)
0
1
Read Timing
J
G
t
3
a
NOTES:
Measurement Conditions:
d(BCLK-RAD)
o r
0 -
n
3 .
1. Values guaranteed only when the microcomputer is used independently.
1
u
2. Varies with operation frequency:
• V
• Input high and low voltage: V
• Output high and low voltage: V
, 1
4
p
1
A maximum of 35ns is guaranteed for the following combinations.
CC
CC
(
2
t
t
t
t
t
t
t
t
M
d(BCLK-RAS)
d(BCLK-CAS)
d(BCLK-CAD)
ac4(RAS-DB)
ac4(CAS-DB)
ac4(CAD-DB)
h(RAS-RAD)
RP
=4.2 to 5.5V
0
18ns.max
=5V Timing Diagram (4)
0
3
=(tcyc/2 x 3-20)ns.min
6
2
C
Row address
tcyc
t
h(BCLK-RAD)
t
8 /
Page 59
h(RAS-RAD)
, 3
=(tcyc/2-13)ns.min
=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states)
=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states)
=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states)
t
-3ns.min
+ t
+ t
+ t
d(BCLK-RAS)
18ns.max
M
su(DB-BCLK)
su(DB-BCLK)
su(DB-BCLK)
3
2
C
f o
(2)
8 /
(1)
9
3
t
1
) T
d(BCLK-CAD)
Hi-Z
18ns.max
IH
=2.5V, V
OH
t
=2.0V, V
ac4(RAS-DB)
t
d(BCLK-CAS)
(1)
18ns.max
IL
t
=0.8V
Column address
ac4(CAD-DB)
OL
t
=0.8V
ac4(CAS-DB)
(2)
(1)
26ns.min
t
su(DB-BCLK)
(2)
(1)
(2)
t
h(BCLK-CAD)
-3ns.min
t
-3ns.min
t
-3ns.min
h(BCLK-RAS)
h(BCLK-CAS)
t
h(CAS-DB)
0ns.min
t
RP
(2)
Vcc=5V

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