MAXQ610A-0000+ Maxim Integrated Products, MAXQ610A-0000+ Datasheet - Page 16
![IC MCU 16BIT 64K IR MOD 32TQFN](/photos/29/0/290079/so8_sml.jpg)
MAXQ610A-0000+
Manufacturer Part Number
MAXQ610A-0000+
Description
IC MCU 16BIT 64K IR MOD 32TQFN
Manufacturer
Maxim Integrated Products
Series
MAXQ™r
Datasheets
1.MAXQ610A-0000.pdf
(28 pages)
2.MAXQ610A-0000.pdf
(29 pages)
3.MAXQ610A-0000.pdf
(23 pages)
Specifications of MAXQ610A-0000+
Core Processor
RISC
Core Size
16-Bit
Speed
12MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Infrared, Power-Fail, POR, WDT
Number Of I /o
20
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
32-TQFN Exposed Pad
Processor Series
MAXQ610
Core
RISC
Data Bus Width
16 bit
Data Ram Size
2 KB
Interface Type
SPI, USART
Maximum Clock Frequency
12 MHz
Number Of Timers
4
Operating Supply Voltage
1.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Controller Family/series
MAXQ
No. Of I/o's
24
Ram Memory Size
2048Byte
Cpu Speed
12MHz
No. Of Timers
2
Embedded Interface Type
JTAG, SPI, USART
Rohs Compliant
Yes
Number Of Programmable I/os
32
Development Tools By Supplier
MAXQ610-KIT
Package
32TQFN EP
Family Name
MAXQ
Maximum Speed
12 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
90-M6800+B01
16-Bit Microcontroller with Infrared Module
Figure 4. External IRTXM (Modulator) Output
Figure 5. IR Capture
When configured in receive mode (IRMODE = 0), the IR
hardware supports the IRRX capture function. The
IRRXSEL[1:0] bits define which edge(s) of the IRRX pin
should trigger IR timer capture function.
The IR module starts operating in the receive mode
when IRMODE = 0 and IREN = 1. Once started, the IR
timer (IRV) starts up counting from 0000h when a quali-
16
______________________________________________________________________________________
IR INTERRUPT
IRV INTERVAL
IRTXPOL = 1
IRTXPOL = 0
IRCLK
IRRX PIN
IRDATA
IRTXM
IRTXM
1
IRMT
IRCAH + 1
CARRIER GENERATION
0
IRMT
EDGE DETECT
IRCAL + 1
1
IR Receive
IRCFME
0
1
0
fied capture event as defined by IRRXSEL happens.
The IRV register is, by default, counting carrier cycles
as defined by the IRCA register. However, the IR carrier
frequency detect (IRCFME) bit can be set to 1 to allow
clocking of the IRV register directly with the IRCLK for
finer resolution. When IRCFME = 0, the IRCA defined
carrier is counted by IRV. When IRCFME = 1, the
IRCLK clocks the IRV register.
CARRIER MODULATION
RESET IRV TO 0000h
1
COPY IRV TO IRMT
0000h
ON EDGE DETECT
IRV
0
IR TIMER OVERFLOW
IR INTERRUPT
IRXRL
1
IRMT
INTERRUPT TO CPU
0
IRDATA
IRMT