UPD78F1146AGA-HAB-AX Renesas Electronics America, UPD78F1146AGA-HAB-AX Datasheet - Page 488
UPD78F1146AGA-HAB-AX
Manufacturer Part Number
UPD78F1146AGA-HAB-AX
Description
MCU 16BIT 78K0R/KX3 64-TQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1142AGA-HAB-AX.pdf
(880 pages)
Specifications of UPD78F1146AGA-HAB-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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486
(4) IIC flag register 0 (IICF0)
This register sets the operation mode of I
IICF0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are
read-only.
The IICRSV bit can be used to enable/disable the communication reservation function.
STCEN can be used to set the initial value of the IICBSY bit.
IICRSV and STCEN can be written only when the operation of I
register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read.
Reset signal generation clears this register to 00H.
Remark
Condition for clearing (ACKD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (STD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (SPD0 = 0)
• At the rising edge of the address transfer byte’s first
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
ACKD0
following address transfer
clock following setting of this bit and detection of a
start condition
SPD0
STD0
0
1
0
1
0
1
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
Acknowledge was not detected.
Acknowledge was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Figure 12-7. Format of IIC Status Register 0 (IICS0) (3/3)
Bit 7 of IIC control register 0 (IICC0)
CHAPTER 12 SERIAL INTERFACE IIC0
User’s Manual U17854EJ9V0UD
2
C and indicates the status of the I
Detection of acknowledge (ACK)
Detection of start condition
Detection of stop condition
Condition for setting (ACKD0 = 1)
• After the SDA0 line is set to low level at the rising
Condition for setting (STD0 = 1)
• When a start condition is detected
Condition for setting (SPD0 = 1)
• When a stop condition is detected
edge of SCL0’s ninth clock
2
C is disabled (bit 7 (IICE0) of IIC control
2
C bus.
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