DS80C320-FNG Maxim Integrated Products, DS80C320-FNG Datasheet - Page 17
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DS80C320-FNG
Manufacturer Part Number
DS80C320-FNG
Description
IC MCU HI SPEED 25MHZ IND 44MQFP
Manufacturer
Maxim Integrated Products
Series
80Cr
Datasheet
1.DS80C323-QND.pdf
(38 pages)
Specifications of DS80C320-FNG
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SIO, UART/USART
Peripherals
Power-Fail Reset, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-MQFP, 44-PQFP
Processor Series
DS80C320
Core
8051
Data Bus Width
8 bit
Program Memory Size
64 KB
Data Ram Size
64 KB
Interface Type
UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.25 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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DS80C320/DS80C323 High-Speed/Low-Power Microcontrollers
POWER MANAGEMENT
The DS80C320/DS80C323 provide the standard Idle and power-down (Stop) modes that are available on
the standard 80C32. However, the device has enhancements that make these modes more useful, and
allow more power saving.
The Idle mode is invoked by setting the LSB of the Power Control register (PCON to 87h). Idle will leave
internal clocks, serial port and timer running. No memory access will be performed so power is
dramatically reduced. Since clocks are running, the Idle power consumption is related to crystal
frequency. It should be approximately one-half the operational power. The CPU can exit the Idle state
with any interrupt or a reset.
The power-down or Stop mode is invoked by setting the PCON.1 bit. Stop mode is a lower power state
than Idle since it turns off all internal clocking. The I
of a standard Stop mode is approximately 1 µA
CC
but is specified in the Electrical Specifications section. The CPU will exit Stop mode from an external
interrupt or a reset condition.
Note that internally generated interrupts (timer, serial port, watchdog) are not useful in Idle or Stop since
they require clocking activity.
IDLE MODE ENHANCEMENTS
A simple enhancement to Idle mode makes it substantially more useful. The innovation involves not the
Idle mode itself, but the watchdog timer. As mentioned above, the Watchdog Timer provides an optional
interrupt capability. This interrupt can provide a periodic interval timer to bring the
DS80C320/DS80C323 out of Idle mode. This can be useful even if the Watchdog is not normally used.
By enabling the Watchdog Timer and its interrupt prior to invoking Idle, a user can periodically come out
of Idle perform an operation, then return to Idle until the next operation. This will lower the overall power
consumption. When using the Watchdog Interrupt to cancel the Idle state, make sure to restart the
Watchdog Timer or it will cause a reset.
STOP MODE ENHANCEMENTS
The DS80C320/DS80C323 provide two enhancements to the Stop mode. As documented above, the
device provides a bandgap reference to determine Power-fail Interrupt and Reset thresholds. The default
state is that the bandgap reference is off when Stop mode is invoked. This allows the extremely low
power state mentioned above. A user can optionally choose to have the bandgap enabled during Stop
mode. This means that PFI and power-fail reset will be activated and are valid means for leaving Stop
mode.
In Stop mode with the bandgap on, I
will be approximately 50A compared with 1A with the bandgap
CC
off. If a user does not require a Power-fail Reset or Interrupt while in Stop mode, the bandgap can remain
turned off. Note that only the most power sensitive applications should turn off the bandgap, as this
results in an uncontrolled power-down condition.
The control of the bandgap reference is located in the Extended Interrupt Flag register (EXIF to 91h).
Setting BGS (EXIF.0) to a 1 will leave the bandgap reference enabled during Stop mode. The default or
reset condition is with the bit at a logic 0. This results in the bandgap being turned off during Stop mode.
Note that this bit has no control of the reference during full power or Idle modes. Be aware that the
DS80C320 and DS80C323 require that the reset watchdog timer bit (RWT;WDCON.0) be set
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