UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 624
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
INTTAB1CC0
INTTAB1OV
CCR0 buffer
CCR1 buffer
TAB1CCR0
TAB1CCR1
The transfer timing is generated when the crest interrupt occurs, the cycle of counting up and counting down
changes, and an asymmetrical triangular wave is output.
Remarks 1. This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 1, TAB1OPT1.TAB1IOE
TOAB1T1
pin output
Transfer
register
register
counter
register
register
signal
(b) Rewriting TAB1CCR0 register
timing
signal
16-bit
When rewriting the TAB1CCR0 register in the intermittent batch mode, the output waveform differs depending
on where the occurrence of the crest or valley interrupt is specified by the interrupt culling setting. The
following figure illustrates the change of the output waveform when interrupts are culled.
2.
L
0000H
0000H
bit = 0, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001.
: Culled interrupt
Figure 11-32. Rewriting TAB1CCR0 Register (When Crest Interrupt Is Set)
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CHAPTER 11 MOTOR CONTROL FUNCTION
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