UPD70F3769GF-GAT-AX Renesas Electronics America, UPD70F3769GF-GAT-AX Datasheet - Page 928
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3769GF-GAT-AX
Manufacturer Part Number
UPD70F3769GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3769GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3769GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 928 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
UF0E0NA
(2) UF0 EP0NAKALL register (UF0E0NA)
Bit position
This register controls NAK to all the requests of Endpoint0. It is also valid for automatically executed requests.
This register can be read or written in 8-bit units.
0
7
0
EP0NKA
Bit name
6
0
This bit controls NAK to a transaction other than a SETUP transaction to Endpoint0
(including an automatically executed request). This bit is manipulated by FW.
This register is used to prevent a conflict between a write access by FW and a read
access from SIE when the data used for an automatically executed request is to be
changed. It postpones reflecting a write access on this bit from FW while an access from
SIE is being made. Before rewriting the request data register from FW, confirm that this
bit has been correctly set to 1.
Setting this bit to 1 is reflected only in the following cases.
Clearing this bit to 0 is reflected immediately, except while an IN token is being received
and a NAK response is being made.
Setting the EP0NKA bit to 1 is reflected in the above four cases during Endpoint0 transfer,
but it is reflected immediately after data has been written to the bit while Endpoint0 is
transferring no data.
5
0
1: Transmit NAK.
0: Do not transmit NAK (default value).
• Immediately after USBF has been reset and a SETUP token has never been
• Immediately after reception of Bus Reset and a SETUP token has never been
• PID of a SETUP token has been detected
• The stage has been changed to the status stage
received
received
4
0
3
0
CHAPTER 20 USB FUNCTION CONTROLLER (USBF)
2
0
Function
1
0
EP0NKA
0
00200002H
Address
Page 928 of 1408
After reset
00H
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