SAB-C165-L25M HA Infineon Technologies, SAB-C165-L25M HA Datasheet - Page 71

• Manufacturer Part Number: SAB-C165-L25M HA
• Description: IC MCU 16BIT MQFP-100-2
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAB-C165-L25M HA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-SQFP
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: 1xASC, 1xSSC
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Packages: PG-MQFP-100
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 2.0 KByte
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: B165L25MHAXP; SABC165L25MHAXT; SP000011593; SP000011594

Figure 21
Notes
1)
2)
3)
4)
5)
6)
7)
Data Sheet
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
The leading edge of the respective command depends on RW-delay.
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill
if READY is removed in response to the command (see Note 4)).
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
The next external bus cycle may start here.
CLKOUT
ALE
Command
RD, WR
Sync
READY
Async
READY
CLKOUT and READY
t
58
3)
Running Cycle
t
t
34
32
t
t
59
30
2)
t
33
t
t
t
31
35
58
3)
t
37
3)
1)
5)
t
t
36
59
67
t
37
t
in order to be safely synchronized. This is guaranteed,
29
t
35
Waitstate
READY
3)
t
36
MUX/Tristate
t
60
4)
see
6)
6)
V2.0, 2000-12
MCT04447
7)
C165