SAK-C164CI-8EM DB Infineon Technologies, SAK-C164CI-8EM DB Datasheet - Page 56
![IC MCU 16BIT 64KB OTP MQFP-80-1](/photos/12/43/124369/sak-c164ci-8em_db_sml.jpg)
SAK-C164CI-8EM DB
Manufacturer Part Number
SAK-C164CI-8EM DB
Description
IC MCU 16BIT 64KB OTP MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C164CI-8EM_CB.pdf
(79 pages)
Specifications of SAK-C164CI-8EM DB
Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, SPI, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
59
Program Memory Size
64KB (64K x 8)
Program Memory Type
OTP
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
ASC, CAN, SSC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
59
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Packages
PG-MQFP-80
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
4.0 KByte
Can Nodes
1
A / D Input Lines (incl. Fadc)
8
Program Memory
64.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
K164CI8EMDBNP
K164CI8EMDBXP
SAK-C164CI-8EMDB
SAK-C164CI-8EMDB
SAK-C164CI-8EMDBIN
SAKC164CI8EMDBX
SP000104059
K164CI8EMDBXP
SAK-C164CI-8EMDB
SAK-C164CI-8EMDB
SAK-C164CI-8EMDBIN
SAKC164CI8EMDBX
SP000104059
Due to this adaptation to the input clock the frequency of
it is locked to
duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and
For a period of
deviation D
where
So for a period of 3 TCLs @ 25 MHz (i.e.
and (3TCL)
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see
Figure 12
Data Sheet
Max. jitter
(
N
N
±26.5
× TCL)
±30
±20
±10
= number of consecutive TCLs and 1 ≤
±1
D
ns
N
N
min
:
1
Approximated Maximum Accumulated PLL Jitter
f
= 3TCL
min
OSC
This approximated formula is valid for
1
N
< –
=
. The slight variation causes a jitter of
× TCL the minimum value is computed using the corresponding
N
N
< –
NOM
× TCL
40 and 10 MHz
10
- 1.288 ns = 58.7 ns (@
NOM
- D
< –
Figure
N
f
CPU
; D
20
N
< –
N
52
25 MHz.
[ns] = ±(13.3 +
= 3): D
12).
N
3
≤ 40.
f
CPU
= (13.3 +
30
= 25 MHz).
f
CPU
N
f
CPU
× 6.3)/
3
is constantly adjusted so
× 6.3)/25 = 1.288 ns,
which also effects the
f
CPU
40
[MHz],
C164CL/SL
V2.0, 2001-05
C164CI/SI
Figure
MCD04455
10 MHz
16 MHz
20 MHz
25 MHz
12).
N