PIC14000/JW Microchip Technology, PIC14000/JW Datasheet
PIC14000/JW
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PIC14000/JW Summary of contents
Page 1
... Multi-segment programmable code-protection • Selectable oscillator options - Internal 4 MHz oscillator - External crystal oscillator • Serial in-system programming (via two pins) 1996 Microchip Technology Inc. This document was created with FrameMaker PIC14000 Pin Diagram PDIP, SOIC, SSOP, Windowed CERDIP RA1/AN1 • ...
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... However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document. DS40122B-page )........................................................................................ 41 Preliminary 1996 Microchip Technology Inc. ...
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... Upon detecting the low voltage con- dition, the PIC14000 can be instructed to save its oper- ating state then enter an idle state. 1996 Microchip Technology Inc. This document was created with FrameMaker The internal band-gap reference is used for calibrating the measurements of the analog peripherals. The calibration factors are stored in EPROM and can be used to achieve high measurement accuracy ...
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... PIC14000 NOTES: DS40122B-page 4 Preliminary 1996 Microchip Technology Inc. ...
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... OTP devices but with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround ...
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... PIC14000 NOTES: DS40122B-page 6 Preliminary 1996 Microchip Technology Inc. ...
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... The PIC14000 contains an 8-bit ALU and working register. The ALU performs arithmetic and Boolean functions between data in the working register and any register file. 1996 Microchip Technology Inc. This document was created with FrameMaker The ALU is capable of addition, subtraction, shift, and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement ...
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... Watchdog W reg Timer Low Voltage Detector Timer0 Slope A/D Serial Port SUM CDAC Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3 PORTC RC0/REFA RC1/CMPA RC2 RC3/T0CKI RC4 RC5 RC6/SCLA RC7/SDAA PORTD RD0/SCLB RD1/SDAB RD2/CMPB RD3/REFB RD4/AN4 RD5/AN5 RD6/AN6 RD7/AN7 1996 Microchip Technology Inc. ...
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... ST/SM RD1/SDAB 5 I/O ST/SM RD2/CMPB 4 I/O-PU AN/ST 1996 Microchip Technology Inc. Pin Type Input Output AN A/D ramp current source output. Normally connected to external capacitor to generate a linear voltage ramp. CMOS Analog input channel 0. This pin can also serve as a general-purpose I/O. CMOS Analog input channel 1 ...
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... Master clear (reset) input / programming voltage input. This pin is an active low reset to the device. Positive supply connection Return supply connection - 1.0V when outputting a logical ‘1’ This pin may be pulled above the supply rail (to 6.0V maximum). Preliminary Description 1996 Microchip Technology Inc. ...
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... All instructions are single cycle, except for program branches. These take two cycles since the fetched instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 1996 Microchip Technology Inc. 3.2 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, four Q2, Q3 and Q4) ...
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... PIC14000 NOTES: DS40122B-page 12 Preliminary 1996 Microchip Technology Inc. ...
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... Calibration Space (64 words) 0FFFh 1000h 20FFh 1996 Microchip Technology Inc. This document was created with FrameMaker 4.1.1 CALIBRATION SPACE The calibration space is not used for instructions. This section stores constants and factors for the arithmetic calculations to calibrate the analog measurements. ...
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... PIE1 8Ch 8Dh PCON 8Eh SLPCON 8Fh 90h 91h 92h 2 93h I CADD 94h 2 I CSTAT 95h 96h 97h 98h 99h 9Ah PREFA 9Bh PREFB 9Ch CMCON 9Dh MISC 9Eh ADCON1 9Fh A0h General Purpose Register (96 Bytes) FF 1996 Microchip Technology Inc. ...
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... POR value and should not be overwritten with any value Reserved indicates reserved register and should not be overwritten with any value * indicates registers that can be addressed from either bank 1996 Microchip Technology Inc. The special registers are classified into two sets. Special registers associated with the “core” functions are described in this section ...
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... I CSEL SMBUS PCFG3 Preliminary Bit 2 Bit 1 Bit 0 PS2 PS1 PS0 T0IF r r RCIE ADCIE OVFIE — POR LVD CMOFF TEMPOFF ADOFF R PRA2 PRA1 PRA0 PRB2 PRB1 PRB0 CMAOUT CMAOE CPOLA INCLKEN OSC2 OSC1 PCFG2 PCFG1 PCFG0 1996 Microchip Technology Inc. ...
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... No carry-out from the most significant bit of the result. Note: For Borrow the polarity is reversed. 1996 Microchip Technology Inc recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the bits from the STATUS register ...
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... RCPU: PORTC pull-up enable 1 = PORTC pull-ups are disabled overriding any port latch value (RC<5:0> only PORTC pull-ups are enabled by individual port-latch values (RC<5:0>) Preliminary Writable Readable Unimplemented. Read as '0' WDT RATE 128 1996 Microchip Technology Inc. ...
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... R/W r GIE PEIE T0IE r T0IF bit7 1996 Microchip Technology Inc. Note: The T0IF will be set by the specified condition even if the corresponding Inter- rupt Enable Bit is cleared (interrupt disabled) or the GIE bit is cleared (all interrupts interrupt, clear the interrupt flag, to ensure ...
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... Disable PBTN interrupt on OSC1/PBTN Unimplemented. Read as ‘0’ Unimplemented. Read as ‘0’ CMIE: Programmable Reference Comparator Interrupt Enable 1 = Enable programmable reference comparator trip 0 = Disable programmable reference comparator trip Preliminary PIE1 W: Writable 8Ch R: Readable 00h U: Unimplemented, read as '0' 1996 Microchip Technology Inc. ...
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... CMIF — PBIF I — CIF RCIF bit7 1996 Microchip Technology Inc. Note: These bits will be set by the specified condition, even if the corresponding Interrupt Enable bit is cleared (interrupt disabled) or the GIE bit is cleared (all interrupts disabled). Before enabling an interrupt, the user may wish to clear the corresponding interrupt fl ...
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... Unimplemented. Read as ‘0’ Unimplemented. Read as ‘0’ Unimplemented. Read as ‘0’ Unimplemented. Read as ‘0’ Unimplemented. Read as ‘0’ Reserved. Bit 7 is reserved. This bit should be programmed as ‘0’ . Preliminary W: Writable R: Readable 8Eh U: Unimplemented, read as ‘0’ 1996 Microchip Technology Inc. ...
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... The tenth push overwrites the second push (and so on). 1996 Microchip Technology Inc. Note 1: There are no STATUS bits to indicate stack conditions. ...
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... CONTINUE: 0 IRP bank select not used 7F Bank 1 Bank 2 Bank 3 Preliminary INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing 7 FSR 00 location select 1996 Microchip Technology Inc. ...
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... CK Q TRISA Read PORTA To A/D Converter Note: I/O pins have protection diodes to V 1996 Microchip Technology Inc. This document was created with FrameMaker Note: On Reset, PORTA is configured as analog inputs The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. ...
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... RC<7:4> are OR’ed together to assert the RCIF flag (PIR1 register<2>) and cause a CPU interrupt, if enabled. Note: If the 2 (I CCON<5>, address 14h), RC<7:6> are automatically interrupt-on-change comparison. Preliminary Bit 1 Bit 0 RA1/AN1 RA0/AN0 R/W R function is enabled, excluded from the 1996 Microchip Technology Inc. ...
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... Set RCIF Note: I/O pins have protection diodes to V 1996 Microchip Technology Inc. The TRISC register controls the direction of the PORTC pin. A ‘1’ in each location configures the corresponding port pin as an input. Upon reset, this register sets to FFh, meaning all PORTC pins are ini- tially inputs. The data register should be initialized prior to confi ...
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... Port Latch = ‘1’ and TRISC = ‘1’ enables weak pull-up if RCPU = ‘0’ in OPTION register. DS40122B-page 28 RCPU CMAOE OPTION<7> CMCON<1> Must clear TRISC<0> to disable pull-up when used as an analog output Schmitt Trigger CK Q Input Buffer Read TRISC From other PORTC pins EN and Preliminary Comment P I/O Pin Read PORTC 1996 Microchip Technology Inc. ...
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... Port Latch =‘1’ and TRISC =‘1’ enables weak pull-up if RCPU =‘0’ in OPTION register the CMAOE bit (CMCON<1>) is set to‘1’, RC0 becomes REFA, RC1 becomes CMPA, ignoring the PORTC<1:0> data and TRISC<1:0> register settings. 1996 Microchip Technology Inc ...
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... C interface. Also is the serial programming data line interface. Also is the serial programming clock. This pin . T0CKI is enabled as TMR0 clock via the OPTION register Preliminary Bit 2 Bit 1 Bit 0 RC2 RC1/CMPA RC0/REFA R/W R/W R which is disabled which is disabled mode 1996 Microchip Technology Inc. ...
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... Control direction on pin RC1/CMPA (has no effect if the CMAOE bit is set pin is an output 1 = pin is an input B0 TRISC0 Control direction on pin RC0/REFA (has no effect if the CMAOE bit is set pin is an output 1 = pin is an input U= unimplemented unknown. 1996 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 TRISC5 TRISC4 TRISC3 R/W R/W ...
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... If CMBOE (CMCON<5>) is set to ‘1’, RD2 becomes CMPB, RD3 becomes REFB, ignoring the PORTD<3:2> data and TRISD<3:2> register settings. DS40122B-page I/O Pin Analog Input Mode Read TRISD Schmitt Trigger Input Buffer and Schmitt Trigger Input Buffer CK Q Read TRISD Read PORTD Preliminary . SS I/O Pin 1996 Microchip Technology Inc. ...
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... R/W R/W POR value xxh X X Bit Name B7 RD7/AN7 RD6/AN6 B6 B5 RD5/AN5 RD4/AN4 B4 B3 RD3/REFB B2 RD2/CMPB B1 RD1/SDAB B0 RD0/SCLB Legend unimplemented, read as ‘0’ unknown. 1996 Microchip Technology Inc CCON<5> Read TRISD Schmitt Trigger Input Buffer and V . These pins do not have a P-channel pull-up. ...
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... Control direction on pin RD1/SDAB: B1 TRISD1 0 = pin is an output 1 = pin is an input Control direction on pin RD0/SCLB: B0 TRISD0 0 = pin is an output 1 = pin is an input DS40122B-page 34 Bit 5 Bit 4 Bit 3 TRISD5 TRISD4 TRISD3 R/W R/W R Preliminary Bit 2 Bit 1 Bit 0 TRISD2 TRISD1 TRISD0 R/W R/W R 1996 Microchip Technology Inc. ...
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... Select Bank1 MOVLW 0xFF ; Value used to initialize ; data direction MOVWF TRISD ; Set RD<7:0> as inputs 1996 Microchip Technology Inc. 5.4 I/O Programming Considerations 5.4.1 BI-DIRECTIONAL I/O PORTS Reading the port register reads the values of the port pins. Writing to the port register writes the value to the port latch ...
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... CPU rather than the new state. When in doubt better to separate these instructions with a NOP or another instruction not accessing this I/O port MOVF PORTC, W NOP Read PORTC Port pin sampled here Execute MOVF PORTC, W PORTC Preliminary NOP Execute NOP 1996 Microchip Technology Inc. ...
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... PSA Enable Watchdog Timer WDT HIBERNATE Enable Bit 1996 Microchip Technology Inc. This document was created with FrameMaker • 8-bit timer • Readable and writable (file address 01h) • 8-bit software programmable prescaler • Interrupt on overflow from FFh to 00h Figure 6 simplified block diagram of the Timer0 module ...
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... NT0 NT0+1 NT0+2 Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2 PC+4 PC+5 PC+6 MOVF TMR0,W NT0+1 Read TMR0 Read TMR0 reads NT0 reads NT0 + 01h 02h 0004h 0005h Inst (0004h) Inst (0005h) Dummy cycle Inst (0004h) 1996 Microchip Technology Inc. ...
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... External clock if no prescaler selected, Prescaler output otherwise. 3. The arrows indicate the points in time where sampling occurs. 1996 Microchip Technology Inc. 6.2.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented ...
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... Preliminary CHANGING PRESCALER (WDT TIMER0) ;Clear WDT and ;prescaler ;Select TMR0, new ;prescale value and ;clock source Power-on Reset Value xxxx xxxx 1111 1111 0000 000x Bit 2 Bit 1 Bit 0 T0IF r r PS2 PS1 PS0 TRISC2 TRISC1 TRISC0 1996 Microchip Technology Inc. ...
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... SCL S Start Change Condition of Data Allowed 1996 Microchip Technology Inc. This document was created with FrameMaker the I C interface protocol each device has an address. When a master wishes to initiate a data transfer, it first transmits the address of the device that it wishes to talk to. All devices “listen” to see if this is their address. Within this address, a bit specifi ...
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... Indicates that a stop bit has been detected last Stop bit was not detected last Data/Address bit 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was address Unimplemented: read as ‘0’ Preliminary 2 CADD 2 CEN is cleared) 2 CEN is cleared) 1996 Microchip Technology Inc. ...
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... FIGURE 7-3: I CCON PORT CONTROL REGISTER R/W R/W R/W R/W R/W R WCOL I COV I CEN CKP I CM3 I CM2 bit7 1996 Microchip Technology Inc. R/W R/W 2 Register: I CCON CM1 I CM0 Address: 14h POR value: 00h bit0 CM<3:0> mode select 2 0110 = I C slave mode, 7-bit address ...
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... The more complex Slave is the 10-bit address with a R/W bit (Figure 7-5). For 10-bit address format, two bytes must be transmitted with the first five bits specifying this 10-bit address. Preliminary 2 C Devices 2 CADD register, the 1996 Microchip Technology Inc. ...
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... SCL Start Address Condition 1996 Microchip Technology Inc. accomplished by setting SMHOG (MISC<7>) high. Clearing MISC<7> will resume the data transfer. Figure 7-7 shows a data transfer waveform. Figure 7-8 and Figure 7-9 show master-transmitter and generates an master-receiver data transfer sequences. ...
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... Sr = repeated may change at this point START condition A Data A Data A/A Sr Slave Address first 7 bits (read) Preliminary R/W A1 Slave Address A2 second byte Data A/A P R/W A1 Slave Address A2 second byte R/W A3 Data A Data A P R/W A Data A Data A P 1996 Microchip Technology Inc. ...
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... The first device to complete its high period will pull the SCL line low. The SCA line high time is determined by the device with the shortest high period. This is shown in the Figure 7-12. 1996 Microchip Technology Inc. FIGURE 7-11: MULTI-MASTER ARBITRATION (2 MASTERS) DATA 1 ...
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... Preliminary Internal data bus Write Addr_Match Set, Reset S, P bits 2 (I CSTAT Reg mode with the I CEN bit set, forces 2 CSR register shifts the 2 CBUF and PIR1<3> 1996 Microchip Technology Inc. ...
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... COV 1996 Microchip Technology Inc. In this case, the CBUF, but the I happens when a data transfer byte is received, given the status of the BF and I show the conditions where user software did not properly clear the overflow condition. The BF flag is cleared by reading the I ...
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... Cleared in software 2 I CBUF is read Preliminary 2 CIF CIF 2 CIF and 2 CIF. 2 CSTAT 2 CSTAT<0> COV bit (I CCON<6>) is set 2 CBUF is read. Receiving Data ACK Bus Master terminates transfer 2 I COV is set 2 because I CBUF is still full. ACK is not sent. 1996 Microchip Technology Inc. ...
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... S Data in sampled 2 I CIF (PIR1<3> CSTAT<0>) 2 CKP (I CCON<4>) 1996 Microchip Technology Inc CIF interrupt is generated for each data transfer 2 byte. The I CIF bit must be cleared in software, and the 2 I CSTAT register is used to determine the status of the 2 CSTAT 2 byte. The I CIF bit is set on the falling edge of the ninth clock pulse ...
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... TRISC3 TRISD5 TRISD4 TRISD3 C module. Preliminary 2 C bus may 2 C interrupt will generate the Bit 2 Bit 1 Bit 0 T0IF r r RCIF ADCIF OVFIF RCIE ADCIE OVFIE CM2 I CM1 I CM0 R INCLKEN OSC2 OSC1 TRISC2 TRISC1 TRISC0 TRISD2 TRISD1 TRISD0 1996 Microchip Technology Inc. ...
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... Writes to this location affect the OSC2 pin in IN mode. Reads return the value of the output latch. OSC1 input port bit (available in IN mode only). B0 OSC1 Reads from this location return the status of the OSC1 pin in IN mode. Writes have no effect. 1996 Microchip Technology Inc. Bit 5 Bit 4 Bit CSEL ...
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... PRIOR_ADDR_MATCH = FALSE; } DS40122B-page IDLE_MODE, RCV_MODE OR XMIT_MODE Set interrupt Send ACK = 0; set XMIT_MODE; } else if (R set RCV_MODE; End of transmission; Go back to IDLE_MODE; { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (I2CADD not updated) Hold SCL low; Clear Set RCV_MODE; } Preliminary 1996 Microchip Technology Inc. ...
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... CIF = 1 E/DRIVE SCL LOW SCL = 0 SCL = 1 1996 Microchip Technology Inc. • A mechanism to stretch the I been implemented to support SMBus slave transactions. The SMHOG bit (MISC<7>) allows hardware to automatically force and hold the I clock line low when a data byte has been received. This prevents the SMBus master from overfl ...
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... PIC14000 NOTES: DS40122B-page 56 Preliminary 1996 Microchip Technology Inc. ...
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... An interrupt is generated to the CPU if enabled. Note: The A/D timer continues to run following a capture event. 1996 Microchip Technology Inc. This document was created with FrameMaker The maximum A/D timer count is 65,536. It can be clocked by the on-chip or external oscillator MHz oscillation frequency, the maximum conversion time is 16.38 ms for a full count. A typical conversion should complete before full-count is reached. A timer overfl ...
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... RA0/AN0 ADOFF ADTMRH ADTMRL (OVFIF, PIR1<0>) A/D Capture ADCAPH ADCAPL A/D Capture Interrupt (ADCIF, PIR1<1>) Note 1: All current sources are disabled if ADRST = ‘1’ Note 2: Approximately 3.5 microsecond time constant Preliminary Timer Overflow Internal Data Bus 1996 Microchip Technology Inc. ...
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... POR value 00h 0 FIGURE 8-6: A/D CAPTURE REGISTER (HIGH BYTE) 16h Bit 7 Bit 6 ADCAPH b15 b14 Read/Write R/W R/W POR value 00h 0 Legend: U= unimplemented unknown. 1996 Microchip Technology Inc. ADTMR INCREMENTS XX+1 XX+2 XX+3 XX+8 XX+9 COMPARE XX Bit 5 Bit 4 Bit R/W R/W R/W ...
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... RA1/AN1 pin 0 RA2/AN2 pin 1 RA3/AN3 pin 0 Bandgap reference voltage 1 Slope reference SREFHI 0 Slope reference SREFLO 1 Internal temperature sensor 0 Programmable reference A output 1 Programmable reference B output 0 RD4/AN4 pin 1 RD5/AN5 pin 0 RD6/AN6 pin 1 RD7/AN7 pin 0 Reserved 1 Reserved Preliminary positive input. Four 1996 Microchip Technology Inc. ...
Page 61
... A 1996 Microchip Technology Inc. The programmable current source output is tied to the CDAC pin and is used to charge an external capacitor to generate the ramp voltage for the A/D comparator. (Refer to Figure 8-1.) This capacitor should have a low voltage-coefficient as found in teflon, polypropylene, or polystyrene capacitors, for optimum results ...
Page 62
... A/D Zero Select Control. (Refer to Section 9.2) B0 ADZERO 1 = Enable zeroing operation on RA1/AN1 and RD5/AN5 0 = Normal operation (sample RA1/AN1 and RD5/AN5 pins) DS40122B-page 62 Bit 5 Bit 4 Bit 3 Bit 2 ADCS1 ADCS0 — AMUXOE R/W R Preliminary Bit 1 Bit 0 ADRST ADZERO R/W R 1996 Microchip Technology Inc. ...
Page 63
... PCFG2 (See Table 8-5) PCFG1 PORTA Configuration Selects B1-B0 PCFG0 (See Table 8-5) TABLE 8-5: PORTA AND PORTD CONFIGURATION ADCON1<1:0> ADCON1<3:2> Legend Analog input Digital I/O 1996 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 PCFG3 R/W R/W R/W R RA0/AN0 RA1/AN1 RD4/AN4 RD5/AN5 ...
Page 64
... Source Output Capacitor (Volts) ( amps) (Farads) 3.5 24.75 1.17E-07 3.5 24.75 2.93E-08 3.5 24.75 7.31E-09 1.5 24.75 2.73E-07 1.5 24.75 6.83E-08 1.5 24.75 1.71E-08 Preliminary CDAC CDAC Capacitor Nearest Standard Value .1uF .022uF 6800pF 0.22 F 68nF 15nF 1996 Microchip Technology Inc. ...
Page 65
... A/D readings. Under no con- ditions should the pin voltage fall below -0.5V. 1996 Microchip Technology Inc. This document was created with FrameMaker 9.2.1 ZEROING/FILTERING SWITCHES The RA1/AN1 and RA5/AN5 inputs also have a matched pair of pass gates useful for current-measure- ment applications ...
Page 66
... C and the temperature coefficient values are stored in the calibration space EPROM (See Table 4-2). To enable the temperature sensor, the TEMPOFF bit (SLPCON<1>) must be cleared. and K cal- BG Preliminary RA1/AN1 only SUM External Capacitor (Optional) To A/D mux, programmable reference comparators 1996 Microchip Technology Inc. ...
Page 67
... CMIE (PIE1<7>) must also be set to enable the com- parator interrupt. In addition, the global interrupt enable and peripheral interrupt enable bits INTCON<7:6> must also be set. This comparator interrupt is level sen- sitive. 1996 Microchip Technology Inc. ADOFF (SLPCON<0> The comparator RC1/CMPA or RD2/CMPB pins by setting the CMAOE (CMCON< ...
Page 68
... For best accuracy, the A/D should be used to peri- odically calibrate the references to the desired set-point. CMOFF Fine Tune Adjust Analog Mux (1-of-8) PREFx<2:0> To CMxOUT bit, CMCON register + CPOLx From Other Comparator Preliminary RC0/REFA or RD3/REFB CMxOE To A/D Converter RC1/CMPA or RD2/CMPB CMIF bit PIR1<7> 1996 Microchip Technology Inc. ...
Page 69
... TABLE 9-1: PROGRAMMABLE REFERENCE COARSE RANGE SELECTION Upper Middle Lower 1996 Microchip Technology Inc. PREFx<7:3> Preliminary PIC14000 Nominal Output Voltage Range (V) 0.8000 - 0.8500 0.7500 - 0.8000 0.7000 - 0.7500 0.6500 - 0.7000 0.6000 - 0.6500 0.5500 - 0.6000 0.5450 - 0.5500 0.5400 - 0.5450 0.5350 - 0.5400 0.5300 - 0.5350 ...
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... REFERENCE FINE RANGE SELECTION Fractional Value Of The PREFx<2:0> Coarse Range FIGURE 9-4: PROGRAMMABLE REFERENCE TRANSFER FUNCTION Upper Range 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 DS40122B-page 70 1 Middle Range 00 PREFx Value (hex) Preliminary Lower Range 1996 Microchip Technology Inc. ...
Page 71
... Comparator A output is available on RC1/CMPA pin and Reference A output is B1 CMAOE available on RC0/REFA pin RC0/REFA and RC1/CMPA assume normal PORTC function. Comparator A Polarity Bit B0 CPOLA 1 = Invert the output of comparator not invert the output of comparator A. 1996 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 CMBOE CPOLB U CMAOUT R/W R/W — ...
Page 72
... See Table 9-1 and Table 9-2 for decoding. Bit 5 Bit 4 Bit 3 Bit 2 PRB5 PRB4 PRB3 PRB2 R/W R/W R/W R Function Programmable Reference B Voltage Select Bits. See Table 9-1 and Table 9-2 for decoding. Preliminary Bit 1 Bit 0 PRA1 PRA0 R/W R Bit 1 Bit 0 PRB1 PRB0 R/W R 1996 Microchip Technology Inc. ...
Page 73
... FET as shown in Figure 9-8. This cir- cuit will provide a VDD of about 5V, after the voltage drop across the FET. FIGURE 9-8: VOLTAGE REGULATOR CIRCUIT PIC14000 1-10 A recommended 6V Typical 1996 Microchip Technology Inc. V REG N-FET (enhancement Optional External Voltage Regulator (Not required for supply voltages below 6 ...
Page 74
... PIC14000 NOTES: DS40122B-page 74 Preliminary 1996 Microchip Technology Inc. ...
Page 75
... Reserved Oscillator Selection Bit B0 FOSC oscillator (internal oscillator (crystal/resonator) 1996 Microchip Technology Inc. This document was created with FrameMaker • Interrupts • Watchdog Timer (WDT) • SLEEP and HIBERNATE modes • Code protection • In-circuit serial programming These features will be described in the following ...
Page 76
... Function 2 C CLK signal (hold low) when receive data buffer is full (refer transfers while preventing interruptions of A CLK stretch clock and data lines clock and data lines. Preliminary by setting INCLKEN Bit 2 Bit 1 Bit 0 INCLKEN OSC2 OSC1 R/W R 1996 Microchip Technology Inc. ...
Page 77
... Resonators Used: 4 MHz Murata Erie CSA4.00MG 8 MHz Murata Erie CSA8.00MT 16 MHz Murata Erie CSA16.00MX All resonators used did not have built-in capacitors. 1996 Microchip Technology Inc. TABLE 10-2: Mode Freq HS 4 MHz 8 MHz 20 MHz Note : Higher capacitance increases the stability of oscillator but also increases the start-up time ...
Page 78
... The devices all have a MCLR noise filter in the MCLR reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. Enable PWRT Enable OST Preliminary S Chip_Reset R Q 1996 Microchip Technology Inc. ...
Page 79
... If these conditions are not met, the device must be held in reset until the operating conditions are met. For additional information, refer to Application Note AN607, “ Power-up Trouble Shooting .” 1996 Microchip Technology Inc. Meaning Power-On Reset Illegal set on POR Illegal set on POR ...
Page 80
... Addr: 03h 000h 0001 1xxx 000h 0001 1uuu 000h 0001 0uuu 000h 0000 1uuu uuu0 0uuu ( uuu1 0uuu Preliminary POWER-UP MCLR C PIC14000 powers down will limit any current PCON Addr: 8Eh 0--- --0x u--- --ux u--- --ux u--- --ux u--- --ux u--- --ux 1996 Microchip Technology Inc. ...
Page 81
... Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 10-4 for reset value for specific condition. 1996 Microchip Technology Inc. MCLR reset during - normal operation - SLEEP ...
Page 82
... INTCON,GIE ; Disable Global Interrupts BTFSC INTCON,GIE ; Global Interrupts Disabled? GOTO LOOP ; No, try again : ; Yes, continue with program ; Wake-up (If in SLEEP mode) T0IF or terminate long write T0IE PEIF PEIE GIE Preliminary 1996 Microchip Technology Inc. interrupt enable bit is may unintentionally be flow Interrupt to CPU ...
Page 83
... Available only in IN oscillator mode on OSC2. 4. For minimum width spec of PBTN pulse, refer to AC specs. 5. PBIF is enabled to be set anytime during the Q4-Q1 cycles. 1996 Microchip Technology Inc. ware in the interrupt service routine before re-enabling the interrupt. This interrupt can wake up the processor from SLEEP if PBIE bit is set (interrupt enabled) prior to going into SLEEP mode ...
Page 84
... W to TEMP register, could be any bank ;Swap status to be saved into W ;Change to bank zero, regardless of current bank ; ;Save status to bank zero STATUS_TEMP register ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W Preliminary 1996 Microchip Technology Inc. ...
Page 85
... Timer PSA Enable Watchdog Timer WDT HIBERNATE Enable Bit 1996 Microchip Technology Inc. The WDT can programming the configuration bit WDTE as a ‘0’. Its oscillator can be shut down to conserve battery power by entering Section 10.8.3 for more information on HIBERNATE mode ...
Page 86
... Controlled by TEMPOFF, SLPCON<1> Controlled by REFOFF, SLPCON<5> Controlled by CMOFF, SLPCON<2> Controlled by ADOFF, SLPCON<0> Controlled by ADOFF, SLPCON<0> and ADCON1<7:4> Controlled by ADOFF, SLPCON<0> Controlled by LSOFF, SLPCON<4> Controlled by REFOFF, SLPCON<5> Always ON. Does not consume power if unconnected. Always ON, except in SLEEP/HIBERNATE mode Preliminary 1996 Microchip Technology Inc. ...
Page 87
... A/D conversion complete (comparator trip) inter- rupt. 8. A/D timer overflow interrupt. 1996 Microchip Technology Inc. An external reset on MCLR pin causes a device reset. The other wake-up continuation of program execution. The TO and PD bits in the STATUS register can be used to determine the cause of device reset ...
Page 88
... The A/D module power is off 0 = The A/D module power is on DS40122B-page 88 Bit 5 Bit 4 Bit 3 REFOFF LSOFF OSCOFF R/W R/W R Function function as either analog or digital. level shifted by approximately 0.5V. continue Preliminary Bit 2 Bit 1 Bit 0 CMOFF TEMPOFF ADOFF R/W R/W R 1996 Microchip Technology Inc. ...
Page 89
... RC6/SCL and RC7/SDA pins low while raising the MCLR (V ) pin from becomes the programming clock and RC7 becomes the programmed data. Both RC6 and RC7 are Schmitt trigger inputs in this mode. 1996 Microchip Technology Inc (2) OST Interrupt Latency (Note 2) Processor in SLEEP ...
Page 90
... PIC14000 NOTES: DS40122B-page 90 Preliminary 1996 Microchip Technology Inc. ...
Page 91
... Assigned to < > Register bit field In the set of i talics User defined term (font is courier) 1996 Microchip Technology Inc. This document was created with FrameMaker The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • ...
Page 92
... C 1,2 ffff C 1,2 ffff C,DC,Z 1,2 ffff 1,2 ffff Z 1,2 ffff 1,2 ffff 1,2 ffff 3 ffff 3 ffff C,DC,Z kkkk Z kkkk kkkk TO PD 0100 , kkkk Z kkkk kkkk 1001 kkkk 1000 TO PD 0011 , C,DC,Z kkkk Z kkkk 1996 Microchip Technology Inc. ...
Page 93
... Words: 1 Cycles: 1 Example ADDWF FSR, 0 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0xD9 FSR = 0xC2 1996 Microchip Technology Inc. ANDLW Syntax: k Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: . Words: Cycles: Example ANDWF f,d Syntax: Operands: Operation: ...
Page 94
... NOP is executed instead, making this a 2 cycle . instruction 1 1(2) HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE • • • Before Instruction PC = address HERE After Instruction if FLAG<1> address TRUE if FLAG<1>= address FALSE 1996 Microchip Technology Inc. ...
Page 95
... PC are loaded from PCLATH. CALL is a two cycle instruction. Words: 1 Cycles: 2 Example HERE CALL Before Instruction PC = Address HERE After Instruction PC = Address THERE TOS = Address HERE+1 1996 Microchip Technology Inc. CLRF Syntax: Operands: Operation: Status Affected: Encoding: bfff ffff Description: Words: Cycles: Example FLAG,1 ...
Page 96
... A NOP is executed instead making it a two cycle instruction. 1 1(2) HERE DECFSZ CNT, 1 GOTO LOOP CONTINUE • • • Before Instruction address PC = HERE After Instruction CNT = CNT - 1 if CNT = address CONTINUE if CNT address HERE+1 1996 Microchip Technology Inc. ...
Page 97
... W register the result is placed back in register 'f'. Words: 1 Cycles: 1 Example INCF CNT, 1 Before Instruction CNT = Z = After Instruction CNT = Z = 1996 Microchip Technology Inc. INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example IORLW Syntax: Operands: Operation: Status Affected: Encoding: ...
Page 98
... Z is affected MOVF FSR, 0 After Instruction W = value in FSR register Move label ] MOVWF 127 (W) (f) None 00 0000 1fff ffff Move data from W register to register . ' MOVWF OPTION Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F 1996 Microchip Technology Inc. ...
Page 99
... PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PIC16CXX products, do not use this instruction. 1996 Microchip Technology Inc. RETFIE Syntax: Operands: Operation: Status Affected: 0xx0 0000 Encoding: Description: Words: Cycles: ...
Page 100
... The power-down status bit cleared. Time-out status bit set. Watchdog Timer and its pres- caler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 10.8 for more details SLEEP 1996 Microchip Technology Inc. ...
Page 101
... After Instruction result is zero Example 3: Before Instruction After Instruction W = 0xFF result is nega- tive 1996 Microchip Technology Inc. SUBWF Syntax: Operands: Operation: Status Affected: kkkk kkkk Encoding: Description: Words: Cycles: Example 1: Example 2: Example 3: Preliminary PIC14000 Subtract W from f [ label ] SUBWF f 127 d [0,1] ...
Page 102
... Z 00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f XORWF REG 1 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 1996 Microchip Technology Inc. ...
Page 103
... Microsoft Windows 3.x environment were chosen to best make these fea- tures available to you, the end user compliant version of PICMASTER is available for European Union (EU) countries. 1996 Microchip Technology Inc. This document was created with FrameMaker ICEPIC: Low-cost PIC16CXX In-Circuit 12.3 Emulator ...
Page 104
... PIC12C5XX, PIC14000, PIC16C5X, PIC16CXX, and PIC17CXX families. MPASM offers full featured Macro capabilities, condi- tional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers. Preliminary 1996 Microchip Technology Inc. ...
Page 105
... MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy TECH-MP, edition for imple- menting more complex systems. 1996 Microchip Technology Inc. Both versions include Microchip’s fuzzy LAB stration board for hands-on experience with fuzzy logic systems implementation. ...
Page 106
... TABLE 12-1: DEVELOPMENT TOOLS FROM MICROCHIP 1996 Microchip Technology Inc. Preliminary PIC14000 DS40122B-page 106 ...
Page 107
... This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1996 Microchip Technology Inc. This document was created with FrameMaker and MCLR) ...................................................... -0. ...
Page 108
... Fosc = 4 MHz, V — 1.1 TBD mA Fosc = 4 MHz, V — 2.4 TBD mA Fosc = 4 MHz, V — 1.2 TBD mA Fosc = 4 MHz, V — 10 TBD mA Fosc = 20 MHz measured with internal oscillator active. PD Preliminary + 85 C for industrial and +70 C for commercial Conditions 4 MHz = 1996 Microchip Technology Inc. ...
Page 109
... Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as coming out of the pin. 1996 Microchip Technology Inc. PIC14000 Standard Operating Conditions (unless otherwise stated) ...
Page 110
... C specifications only Hold ST DAT DATA input hold STA START condition DS40122B-page 110 specifications only specifications only) T Time osc OSC1 t0 T0CKI P Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Preliminary 1996 Microchip Technology Inc. ...
Page 111
... All devices are tested to operate at “min.” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. 1996 Microchip Technology Inc ...
Page 112
... PIC14000 FIGURE 13-2: LOAD CONDITIONS Load condition 1 Pin RL = 464 DS40122B-page 112 Load condition Pin V SS for all pins except OSC2 for OSC2 output Preliminary 1996 Microchip Technology Inc. ...
Page 113
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in IN Mode where CLKOUT output 1996 Microchip Technology Inc ...
Page 114
... DS40122B-page 114 Min Typ† Max Units 100 — — 33* ms — -12.6 — %/V — 0.5 — 1024 T ms OSC OSC 28* 72 132* ms 100 ns Preliminary 1996 Microchip Technology Inc. Conditions V = 5V 5V OSC1 period OSC IN osc mode V = 5V ...
Page 115
... T0CKI Low Pulse Width 42 Tt0P T0CKI Period * These parameters are characterized but not tested. † Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. 1996 Microchip Technology Inc Min Typ† No Prescaler 0 20* — ...
Page 116
... KHz mode 600 — — 100 KHz mode 4000 — — ns 400 KHz mode 600 — — Preliminary 83 93 STOP Condition Conditions Only relevant for repeated START condition After this period the first clock pulse is generated 1996 Microchip Technology Inc. ...
Page 117
... This will automatically be the case if the device does not stretch the LOW SU period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T bus specification) before the SCL line is released. 1996 Microchip Technology Inc. 100 90 101 91 ...
Page 118
... THRESHOLD VOLTAGE) OF OSC1 INPUT (IN HS MODE 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00 1.80 1.60 1.40 1.20 1.00 3.0 3.5 DS40122B-page 118 FIGURE 13-10: TYPICAL 4.0 4.5 5.0 V (Volts) DD Preliminary PD3 DETERMINED. DD 5.5 6.0 6.5 1996 Microchip Technology Inc. ...
Page 119
... FIGURE 13-12: TYPICAL OPERATING SUPPLY CURRENT 10,000 1,000 100 10 1 10,000 100,000 FIGURE 13-13: MAXIMUM OPERATING SUPPLY CURRENT 1996 Microchip Technology Inc. FREQ (EXT CLOCK 1,000,000 10,000,000 Frequency (Hz) FREQ (EXT CLOCK, - DETERMINED. Preliminary PIC14000 6.0 5.5 5.0 4.5 4.0 3.5 3 ...
Page 120
... PIC14000 FIGURE 13-14: MAXIMUM I PD1 VS FIGURE 13-15: WATCHDOG TIMER TIME-OUT PERIOD ( -40 -30 -20 -10 DS40122B-page 120 FREQ (EXT CLOCK, - DETERMINED. ) VS. TEMPERATURE (TYPICAL) WDT Temperature ( C) Preliminary V = 100 1996 Microchip Technology Inc. ...
Page 121
... Min, -40˚C 5 (Volts) DD FIGURE 13-17: TRANSCONDUCTANCE (GM OSCILLATOR 9000 8000 7000 6000 5000 4000 3000 2000 1000 (Volts) DD 1996 Microchip Technology Inc. FIGURE 13-18 -10 -15 -20 - FIGURE 13-19 -10 -15 -20 Min @ 85 C -25 Typ @ 25 C -30 -35 -40 Max @ -40 C -45 -50 0 0.5 ...
Page 122
... PIC14000 FIGURE 13-20 3V Min @ - Typ @ Min @ + 0 (Volts) OL DS40122B-page 122 FIGURE 13-21 2 0.5 1 *NOTE: All pins except OSC2 Preliminary 5V Min @ -40 C Typ @ 25 C Min @ +85 C 2.5 3 3.5 4 1 (Volts) OL 1996 Microchip Technology Inc. ...
Page 123
... V CDAC pin voltage = 0V to VDD - 1.4V 0 — VDD-1.4 V — ADCON1<7:4> = 1111b — 0 — A REFOFF = 1, ADOFF = 1 0.92 1.05 1. — 0.2 — From VDDmin to VDDmax 3.2 3.65 4.1 mV/ C Measured from Tmax. Includes calibration tolerance Preliminary Conditions Notes 1111b temperature 1996 Microchip Technology Inc. ...
Page 124
... Programmable Reference(s) Upper Range Output Voltage vo(pref) Coarse Resolution resc(pref) Fine Resolution resf(pref) Middle Range Output Voltage vo(pref) Coarse Resolution resc(pref) Fine Resolution resf(pref) 1996 Microchip Technology Inc. Min. Typ. Max. Units — TBD — — 150 250 A TEMPOFF = 0 — 0 — ...
Page 125
... Tcycs At Power-On Reset and exit from SLEEP — 300 500 A — 0 — A SLEEP mode, OSCOFF = 1 5.2 5.9 6.6 V Measured with Ivreg = — -0.2 — From Tmin to Tmax 1 – Determined by external components — 0 — REG Preliminary Conditions Notes pin is open 1996 Microchip Technology Inc. ...
Page 126
... Output Voltage vo(lvs) Zeroing Mismatch Error zm(lvs) Output Voltage Temperature tc(lvs) Coefficient Output Voltage Supply ss(lvs) Sensitivity Operating Current (network on) idd(lvs) Operating Current (network off) idd(lvs) 1996 Microchip Technology Inc. Min. Typ. Max. Units - Tested at 0.5V common-mode voltage 0 — VDD-1.4 V — ...
Page 127
... Units All parameters calibrated at VDD = 5V unless noted. Accuracy Resolution Units Typ Max 0.015% — .02% — .01% — .02% — 0. 6.7% — Calibrated and Tmax 10.0 kHz 0.14% — 0.5 ms — typical max (TMAX - 25 Preliminary Conditions Notes 3, 5 Conditions Notes C ) 1996 Microchip Technology Inc. ...
Page 128
... FIGURE 14-1: BANDGAP REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE (TYPICAL DEVICES SHOWN) 1.194 1.192 1.190 1.188 1.186 1.184 1.182 1.180 1.178 -40 -30 FIGURE 14-2: PROGRAMMABLE CURRENT SOURCE vs. TEMPERATURE (TYPICAL DEVICES SHOWN) 2.7 2.5 2.3 2.1 1.9 1.7 -40 -30 -20 1996 Microchip Technology Inc. -20 - Temperature ( C) - Temperature ( C) Preliminary PIC14000 70 80 ...
Page 129
... FIGURE 14-4: SLOPE REFERENCE RATIO (K (TYPICAL DEVICES SHOWN) 0.1260 0.1258 0.1256 0.1254 0.1252 0.1250 2.5 3.0 DS40122B-page 129 -20 - Temperature ( C) ) vs. SUPPLY VOLTAGE REF 3.5 4.0 4.5 5.0 Supply Voltage (Volts) Preliminary 100 5.5 6.0 1996 Microchip Technology Inc. ...
Page 130
... FIGURE 14-5: SLOPE REFERENCE RATIO (K (TYPICAL DEVICES SHOWN) 0.1260 0.1258 0.1256 0.1254 0.1252 0.1250 0.1248 0.1246 -40 -20 FIGURE 14-6: PROGRAMMABLE REFERENCE OUTPUT vs. TEMPERATURE (TYPICAL) 0.7 0.6 0.5 0.4 0.3 -40 -30 -20 1996 Microchip Technology Inc. ) vs. TEMPERATURE REF Temperature ( C) Fixed Bandgap Reference Voltage - Temperature ( C) Preliminary PIC14000 80 ...
Page 131
... FIGURE 14-8: INTERNAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE (TYPICAL DEVICES SHOWN) 4.4 4.3 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 -40 -30 -20 DS40122B-page 131 3.0 3.5 4.0 4.5 5.0 Supply Voltage (Volts) - Temperature ( C) Preliminary 5.5 6 100 1996 Microchip Technology Inc. ...
Page 132
... NOTES: 1996 Microchip Technology Inc. Preliminary PIC14000 DS40122B-page 132 ...
Page 133
... APPENDIX A: PIC16/17 MICROCONTROLLERS A.1 PIC14000 Devices 1996 Microchip Technology Inc. This document was created with FrameMaker Preliminary PIC14000 DS40122B-page 133 ...
Page 134
... PIC14000 A.2 PIC16C5X Family of Devices DS40122B-page 134 Preliminary 1996 Microchip Technology Inc. ...
Page 135
... A.3 PIC16CXXX Family of Devices 1996 Microchip Technology Inc. Preliminary PIC14000 DS40122B-page 135 ...
Page 136
... PIC14000 A.4 PIC16C6X Family of Devices DS40122B-page 136 Preliminary 1996 Microchip Technology Inc. ...
Page 137
... A.5 PIC16C7X Family of Devices 1996 Microchip Technology Inc. Preliminary PIC14000 DS40122B-page 137 ...
Page 138
... PIC14000 A.6 PIC16C8X Family of Devices DS40122B-page 138 Preliminary 1996 Microchip Technology Inc. ...
Page 139
... A.7 PIC16C9XX Family Of Devices 1996 Microchip Technology Inc. Preliminary PIC14000 DS40122B-page 139 ...
Page 140
... PIC14000 A.8 PIC17CXX Family of Devices DS40122B-page 140 Preliminary 1996 Microchip Technology Inc. ...
Page 141
... PIC16C710, PIC16C71, PIC16C711, PIC16C83, PIC16CR83, PIC16C84, PIC16C84A, PIC16CR84 PIC16C55, PIC16C57, PIC16CR57B PIC16C62, PIC16CR62, PIC16C62A, PIC16C63, PIC16C72, PIC16C73, PIC16C73A PIC16C64, PIC16CR64, PIC16C64A, PIC16C65, PIC16C65A, PIC16C74, PIC16C74A PIC17C42, PIC17C43, PIC17C44 1996 Microchip Technology Inc socket Package 8-pin 18-pin 20-pin 28-pin 28-pin 40-pin 40-pin ...
Page 142
... PIC14000 NOTES: DS40122B-page 142 Preliminary 1996 Microchip Technology Inc. ...
Page 143
... Fuzzy Logic Dev. System ( fuzzy TECH“-MP) ........... 103, 105 G GOTO Instruction............................................................... 97 I IDLE_MODE ...................................................................... 54 INCF Instruction ................................................................. 97 INCFSZ Instruction ............................................................ 97 Instruction Cycle ................................................................ 11 Instruction Flow/Pipelining ................................................. 11 Instruction Format .............................................................. 91 Instruction Set ADDLW ...................................................................... 93 1996 Microchip Technology Inc. This document was created with FrameMaker ADDWF ...................................................................... 93 ANDLW....................................................................... 93 ANDWF ...................................................................... 93 BCF ............................................................................ 94 BSF............................................................................. 94 BTFSC........................................................................ 94 BTFSS ........................................................................ 95 CALL........................................................................... 95 CLRF .......................................................................... 95 CLRW ......................................................................... 95 CLRWDT ...
Page 144
... Figure 7-8: Master - Transmitter Sequence ................. 46 Figure 7-9: Master - Receiver Sequence ..................... 46 Figure 7-10: Combined Format ...................................... 46 Figure 7-11: Multi-master Arbitration (2 Masters) .......... 47 2 Figure 7-12 Clock Synchronization ......................... 47 2 Figure 7-13 Block Diagram ..................................... 48 2 Figure 7-14 Waveforms For Reception (7-bit Address) ........................................... 50 Preliminary 1996 Microchip Technology Inc. ...
Page 145
... C) .......................................... 119 Figure 13-14: Maximum Freq (Ext clock, PD -40 to +85 C) .......................................... 120 Figure 13-15: PIC14000 Watchdog Timer Time-Out Period (T ) vs. Temperature (Typical) 120 WDT 1996 Microchip Technology Inc. Figure 13-16: WDT Timer Time-out Period vs V Figure 13-17: Transconductance (gm Oscillator Figure 13-18 Figure 13-19: I ...
Page 146
... Reset, Watchdog Timer, Oscillator Start-up Timer And Power-up Timer Requirements .......................................... 114 Table 13-4: Timer0 Clock Requirements .................... 115 2 Table 13- Bus Start/stop Bits Requirements...... 116 2 Table 13- Bus Data Requirements .................... 117 Table A-1: Pin Compatible Devices ........................... 141 DS40122B-page 146 Preliminary 1996 Microchip Technology Inc. ...
Page 147
... CompuServe membership to join Microchip's BBS. There is no charge for connecting to the Microchip BBS. 1996 Microchip Technology Inc. This document was created with FrameMaker The procedure to connect will vary slightly from country to country. Please check with your local CompuServe agent for details if you have a problem ...
Page 148
... Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS40122B-page 148 Total Pages Sent FAX: (______) _________ - _________ N Literature Number: DS40122B Preliminary 1996 Microchip Technology Inc. ...
Page 149
... PART NO. -XX X /XX XXX Pattern: Package: Temperature Range: Frequency Range: Device: 1996 Microchip Technology Inc. This document was created with FrameMaker 3-Digit Pattern Code for QTP (blank otherwise 300 mil PDIP SO = 300 mil SOIC (Gull Wing, 300 mil body 209 mil SSOP ...
Page 150
... PIC14000 NOTES: DS30444C-page 150 Preliminary 1996 Microchip Technology Inc. ...
Page 151
... NOTES: 1996 Microchip Technology Inc. Preliminary PIC14000 DS30444C-page 151 ...
Page 152
... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
Page 153
... Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology Taiwan 11F-3, No. 207 ...