PIC17C756A/CL Microchip Technology, PIC17C756A/CL Datasheet - Page 230
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17C756A/CL
Manufacturer Part Number
PIC17C756A/CL
Description
IC MCU EPROM 16KX16 A/D 68CLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A/CL
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
EPROM
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-CLCC Window, 68-CERQUAD
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 230 of 304
- Download datasheet (6Mb)
PIC17C7XX
TLWT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS30289B-page 230
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
t
RAM
TBLAT
RAM
TBLAT
t
RAM
TBLAT
RAM
TBLAT
Q1
=
=
=
=
=
=
=
=
=
=
register ’f’
Table Latch Write
[ label ] TLWT t,f
0
t
If t = 0,
f
If t = 1,
f
None
Data from file register ’f’ is written into
the 16-bit table latch (TBLAT).
If t = 1; high byte is written
If t = 0; low byte is written
This instruction is used in conjunction
with TABLWT to transfer data from data
memory to program memory.
1
1
TLWT
Read
1010
Q2
0
0xB7
0x0000
0xB7
0x00B7
1
0xB7
0x0000
0xB7
0xB700
[0,1]
f
TBLATL;
TBLATH
255
t, RAM
01tx
(TBLATH = 0x00)
(TBLATL = 0x00)
(TBLATL = 0xB7)
(TBLATH = 0x00)
(TBLATL = 0x00)
(TBLATL = 0x00)
(TBLATH = 0x00)
(TBLATH = 0xB7)
Process
Data
Q3
ffff
TBLATH or
TBLATL
register
Write
Q4
ffff
TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
Before Instruction
After Instruction
operation
Decode
PC = Address (HERE)
If CNT
If CNT
Q1
Q1
No
PC
PC
register ’f’
operation
Test f, skip if 0
[ label ] TSTFSZ f
0
skip if f = 0
None
If ’f’ = 0, the next instruction, fetched
during the current instruction execution,
is discarded and a NOP is executed,
making this a two-cycle instruction.
1
1 (2)
HERE
NZERO
ZERO
Read
0011
Q2
Q2
No
=
=
¼
=
f
2000 Microchip Technology Inc.
255
0x00,
Address (ZERO)
0x00,
Address (NZERO)
TSTFSZ
:
:
0011
operation
Process
Data
Q3
Q3
No
CNT
ffff
operation
operation
Q4
Q4
No
No
ffff
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