PIC18C252/JW Microchip Technology, PIC18C252/JW Datasheet - Page 138
![IC MCU 16x16 A/D 28CDIP](/photos/7/29/72984/150-28-cdip_sml.jpg)
PIC18C252/JW
Manufacturer Part Number
PIC18C252/JW
Description
IC MCU 16x16 A/D 28CDIP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C252/JW
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
EPROM, UV
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-CDIP (0.300", 7.62mm) Window
For Use With
XLT28XP - SOCKET TRANSITION ICE 28DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C252/JW
Manufacturer:
MICROCHIP
Quantity:
4 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 138 of 305
- Download datasheet (6Mb)
PIC18CXX2
14.4.5
In I
located in the lower 7 bits of the SSPADD register
(Figure 14-14). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
FIGURE 14-14:
FIGURE 14-15:
DS39026C-page 136
2
C Master mode, the reload value for the BRG is
BAUD RATE GENERATOR
SDA
SCL
BRG
Value
BRG
Reload
BAUD RATE GENERATOR BLOCK DIAGRAM
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SSPM3:SSPM0
03h
SCL
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
02h
SSPM3:SSPM0
SCL is sampled high, reload takes
place and BRG starts its count.
Reload
Control
01h
CLKOUT
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
Reload
DX-1
remented twice per instruction cycle (T
and Q4 clocks. In I
reloaded automatically. If Clock Arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 14-15).
BRG Down Counter
SSPADD<6:0>
SCL allowed to transition high
03h
2
C Master mode, the BRG is
F
2001 Microchip Technology Inc.
OSC
02h
/4
CY
) on the Q2
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