AT90LS2333-4AI Atmel, AT90LS2333-4AI Datasheet - Page 53

• Manufacturer Part Number: AT90LS2333-4AI
• Description: IC MCU 2K 4MHZ A/D LV IT 32TQFP
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS2333-4AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The ADC is enabled by writing a logical one to the ADC Enable bit, ADEN in ADCSR. The first conversion that is started
after enabling the ADC, will be preceded by a dummy conversion to initialize the ADC. To the user, the only difference will
be that this conversion takes 12 more clock cycles than a normal conversion.
A conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit will stay high as long as the
conversion is in progress and be set to zero by hardware when the conversion is completed. If a different data channel is
selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel
change.
As the ADC generates a 10-bit result, two data registers, ADCH and ADCL, must be read to get the result when the conver-
sion is complete. Special data protection logic is used to ensure that the contents of the data registers belong to the same
result when they are read. This mechanism works as follows:
When reading data, ADCL must be read first. Once ADCL is read, ADC access to data registers is blocked. This means
that if ADCL has been read, and a conversion completes before ADCH is read, none of the registers are updated and the
result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL registers is re-enabled.
The ADC has its own interrupt, ADIF, which can be triggered when a conversion completes. When ADC access to the data
registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result gets lost.
Prescaling
Figure 45. ADC Prescaler
The ADC contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADC accepts
input clock frequencies in the range 50 - 200 kHz. Applying a higher input frequency will result in a poorer accuracy, see
“ADC Characteristics” on page 58.
The ADPS0 - ADPS2 bits in ADCSR are used to generate a proper ADC clock input frequency from any XTAL frequency
above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR.
The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following rising edge of the
ADC clock cycle. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of the conversion. The result
is ready and written to the ADC Result Register after 13 cycles. In single conversion mode, the ADC needs one more clock
cycle before a new conversion can be started, see Figure 47. If ADSC is set high in this period, the ADC will start the new
conversion immediately. In Free Run Mode, a new conversion will be started immediately after the result is written to the
ADC Result Register. Using Free Run Mode and an ADC clock frequency of 200 kHz gives the lowest conversion time, 65
s, equivalent to 15.4 kSPS. For a summary of conversion times, see Table 21.
ADEN
ADPS0
ADPS1
ADPS2
CK
Reset
AT90S/LS2333 and AT90S/LS4433
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
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