AT90S8515-4PC Atmel, AT90S8515-4PC Datasheet - Page 42
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AT90S8515-4PC
Manufacturer Part Number
AT90S8515-4PC
Description
IC MCU 8K FLSH 4MHZ LV 40DIP
Manufacturer
Atmel
Series
AVR® 90Sr
Datasheets
1.AT90S8515-4AC.pdf
(112 pages)
2.AT90S8515-4AC.pdf
(4 pages)
3.AT90S8515-4AC.pdf
(4 pages)
Specifications of AT90S8515-4PC
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Watchdog Timer
Watchdog Timer Control
Register – WDTCR
42
AT90S8515
The Watchdog Timer is clocked from a separate On-chip oscillator that runs at 1 MHz.
This is the typical value at V
V
can be adjusted (see Table 14 for a detailed description). The WDR (Watchdog Reset)
instruction resets the Watchdog Timer. Eight different clock cycle periods can be
selected to determine the reset period. If the reset period expires without another
Watchdog reset, the AT90S8515 resets and executes from the reset vector. For timing
details on the Watchdog reset, refer to page 25.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be
followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 33. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the AT90S8515 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will
not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.
Refer to the description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared
(zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be
followed:
Bit
$21 ($41)
Read/Write
Initial Value
CC
levels. By controlling the Watchdog Timer prescaler, the Watchdog reset interval
R
7
–
0
R
6
–
0
CC
= 5V. See characterization data for typical values at other
R
5
–
0
WDTOE
R/W
4
0
WDE
R/W
3
0
WDP2
R/W
2
0
WDP1
R/W
1
0
WDP0
R/W
0
0
0841G–09/01
WDTCR