PIC16LC773T-I/SO Microchip Technology, PIC16LC773T-I/SO Datasheet - Page 59
![IC MCU OTP 4KX14 A/D PWM 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16LC773T-I/SO
Manufacturer Part Number
PIC16LC773T-I/SO
Description
IC MCU OTP 4KX14 A/D PWM 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC773T-I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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8.1.4
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2,
cast data by the software protocol.
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
FIGURE 8-6:
1999 Microchip Technology Inc.
SCK
(CKP = 0
CKE = 1)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
SDO
(CKE = 1)
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
MASTER MODE
SPI MODE WAVEFORM (MASTER MODE)
bit7
bit7
bit7
bit7
Figure
bit6
bit6
8-5) is to broad-
Advance Information
bit5
bit5
bit4
bit4
Figure
is transmitted first. In master mode, the SPI clock rate
(bit rate) is user programmable to be one of the follow-
ing:
• F
• F
• F
• Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 8.25 MHz.
Figure 8-6
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
bit3
bit3
OSC
OSC
OSC
8-6,
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit2
bit2
Figure
shows the waveforms for Master mode.
CY
)
8-8, and
bit1
bit1
CY
CY
)
)
PIC16C77X
bit0
Figure 8-9
bit0
bit0
bit0
DS30275A-page 59
Next Q4 cycle
after Q2
where the MSb
4 clock
modes
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