PIC16LF871T-I/PT Microchip Technology, PIC16LF871T-I/PT Datasheet - Page 47
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PIC16LF871T-I/PT
Manufacturer Part Number
PIC16LF871T-I/PT
Description
IC MCU FLASH 2KX14 EE A/D 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF871T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
PSP, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
28 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF871T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
5.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Additional information on the Timer0 module is avail-
able in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1:
2003 Microchip Technology Inc.
RA4/T0CKI
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
WDT Enable bit
CLKO (= F
pin
Watchdog
TIMER0 MODULE
Timer
OSC
/4)
T0SE
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
0
1
PSA
M
U
X
0
1
T0CS
M
U
X
0
8-bit Prescaler
8 - to - 1MUX
Time-out
8
M U X
WDT
PRESCALER
1
0
1
PSA
M
U
X
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment either on every rising, or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler is not readable or writable. Section 5.3 details the
operation of the prescaler.
5.1
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module Interrupt Ser-
vice Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut-off during SLEEP.
PSA
Timer0
PS2:PS0
Timer0 Interrupt
Cycles
SYNC
2
PIC16F870/871
Source
Edge
TMR0 Reg
Data Bus
Select
8
DS30569B-page 45
Set Flag Bit T0IF
on Overflow
bit,
T0SE