PIC17LC752T-08/L Microchip Technology, PIC17LC752T-08/L Datasheet - Page 213
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17LC752T-08/L
Manufacturer Part Number
PIC17LC752T-08/L
Description
IC MCU OTP 8KX16 A/D 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Specifications of PIC17LC752T-08/L
Core Processor
PIC
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
16KB (8K x 16)
Program Memory Type
OTP
Ram Size
678 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17LC752T-08/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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INCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2000 Microchip Technology Inc.
Before Instruction
After Instruction
Decode
CNT
Z
C
CNT
Z
C
Q1
=
=
=
=
=
=
register ’f’
Increment f
[ label ]
0
d
(f) + 1
OV, C, DC, Z
The contents of register ’f’ are incre-
mented. If ’d’ is 0, the result is placed in
WREG. If ’d’ is 1, the result is placed
back in register ’f’.
1
1
INCF
Read
0001
Q2
0xFF
0
?
0x00
1
1
f
[0,1]
255
(dest)
INCF f,d
010d
CNT, 1
Process
Data
Q3
ffff
destination
Write to
Q4
ffff
INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
Before Instruction
After Instruction
operation
Decode
PC
CNT
If CNT
If CNT
Q1
Q1
No
PC =
PC =
=
=
=
register ’f’
operation
Increment f, skip if 0
[ label ]
0
d
(f) + 1
skip if result = 0
None
The contents of register ’f’ are incre-
mented. If ’d’ is 0, the result is placed in
WREG. If ’d’ is 1, the result is placed
back in register ’f’.
If the result is 0, the next instruction,
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
1
1(2)
HERE
NZERO
ZERO
Read
0001
Q2
Q2
No
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
f
[0,1]
PIC17C7XX
255
(dest)
INCFSZ
:
:
INCFSZ f,d
111d
operation
Process
Data
Q3
Q3
No
DS30289B-page 213
ffff
CNT, 1
destination
operation
Write to
Q4
Q4
No
ffff
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