PIC18C442T-I/L Microchip Technology, PIC18C442T-I/L Datasheet - Page 220
![IC MCU OTP 8KX16 A/D 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC18C442T-I/L
Manufacturer Part Number
PIC18C442T-I/L
Description
IC MCU OTP 8KX16 A/D 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C242-ISO.pdf
(305 pages)
4.PIC18C242-ISO.pdf
(12 pages)
Specifications of PIC18C442T-I/L
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
16KB (8K x 16)
Program Memory Type
OTP
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
MSSP, SPI, I2C, PSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
8
For Use With
I3DB18C452 - BOARD DAUGHTER ICEPIC3DVA16XL441 - ADAPTER DEVICE ICE 44PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C442T-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC18C242-ISO PDF datasheet #3
- PIC18C242-ISO PDF datasheet #4
- Current page: 220 of 305
- Download datasheet (6Mb)
PIC18CXX2
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39026C-page 218
Q Cycle Activity:
After Interrupt
operation
Decode
PC
W
BSR
STATUS
GIE/GIEH, PEIE/GIEL=
No
Q1
operation
operation
Return from Interrupt
[ label ]
s
(TOS)
1
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged.
GIE/GIEH,PEIE/GIEL.
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
WREG, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
1
2
RETFIE
0000
No
No
Q2
[0,1]
GIE/GIEH or PEIE/GIEL,
WREG,
PC,
1
RETFIE [s]
0000
BSR,
operation
operation
=
=
=
=
No
No
STATUS,
Q3
1
TOS
WS
BSRS
STATUSS
0001
pop PC from
Set GIEH or
operation
stack
GIEL
No
Q4
000s
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
TABLE
Q Cycle Activity:
CALL TABLE
:
ADDWF PCL
RETLW k0
RETLW k1
:
:
RETLW kn
Before Instruction
After Instruction
operation
Decode
WREG
WREG
No
Q1
; WREG contains table
; offset value
; WREG now has
; table value
; WREG = offset
; Begin table
;
; End of table
=
=
operation
Return Literal to WREG
[ label ]
0
k
(TOS)
PCLATU, PCLATH are unchanged
None
WREG is loaded with the eight-bit
literal 'k'. The program counter is
loaded from the top of the stack
(the return address). The high
address latch (PCLATH) remains
unchanged.
1
2
literal ’k’
Read
0000
No
Q2
0x07
value of kn
k
WREG,
2001 Microchip Technology Inc.
255
PC,
RETLW k
1100
operation
Process
Data
No
Q3
kkkk
pop PC from
stack, Write
to WREG
operation
Q4
No
kkkk
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