AT90LS4433-4AI Atmel, AT90LS4433-4AI Datasheet - Page 40
![IC MCU 4K 4MHZ A/D LV 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
AT90LS4433-4AI
Manufacturer Part Number
AT90LS4433-4AI
Description
IC MCU 4K 4MHZ A/D LV 32TQFP
Manufacturer
Atmel
Series
AVR® 90LSr
Datasheet
1.AT90S4433-8AC.pdf
(126 pages)
Specifications of AT90LS4433-4AI
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90LS4433-4AI
Manufacturer:
HYNIX
Quantity:
14
Part Number:
AT90LS4433-4AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Timer/Counter1 Output
Compare Register – OCR1H
and OCR1L
40
AT90S/LS4433
the TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for a
full 16-bit register read operation.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read
and write access. If Timer/Counter1 is written to and a clock source is selected, the
Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-
ten value.
The Output Compare Register is a 16-bit read/write register.
The Timer/Counter1 Output Compare Register contains the data to be continuously
compared with Timer/Counter1. Actions on compare matches are specified in the
Timer/Counter1 Control and Status Register.
Since the Output Compare Register (OCR1) is a 16-bit register, a temporary register
TEMP is used when OCR1 is written to ensure that both bytes are updated simulta-
neously. When the CPU writes the High Byte, OCR1H, the data is temporarily stored in
the TEMP Register. When the CPU writes the Low Byte, OCR1L, the TEMP Register is
simultaneously written to OCR1H. Consequently, the High Byte OCR1H must be written
first for a full 16-bit register write operation.
The TEMP Register is also used when accessing TCNT1 and ICR1. If the main program
and interrupt routines perform access to registers using TEMP, interrupts must be dis-
abled during access from the main program.
Bit
$2B ($4B)
$2A ($4A)
Read/Write
Initial Value
MSB
R/W
R/W
15
7
0
0
R/W
R/W
14
6
0
0
R/W
R/W
13
5
0
0
R/W
R/W
12
4
0
0
R/W
R/W
11
3
0
0
R/W
R/W
10
2
0
0
R/W
R/W
9
1
0
0
LSB
R/W
R/W
8
0
0
0
1042H–AVR–04/03
OCR1H
OCR1L