AT89C55WD-24JC Atmel, AT89C55WD-24JC Datasheet - Page 18

• Manufacturer Part Number: AT89C55WD-24JC
• Description: IC MICRO CTRL 24MHZ 44PLCC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C55WD-24JC

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 20KB (20K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3 x 16 bit
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No RoHS Version Available
• Other names: AT89C55WD24JC

16. Oscillator Characteristics
17. Idle Mode
18. Power-down Mode
18
AT89C55WD
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be
configured for use as an on-chip oscillator, as shown in
ceramic resonator may be used. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven, as shown in
requirements on the duty cycle of the external clock signal, since the input to the internal clock-
ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low
time specifications must be observed.
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special functions regis-
ters remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-
gram execution from where it left off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when idle mode is terminated by a reset, the instruction following the one that invokes
idle mode should not write to a port pin or to external memory.
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the Power-down mode is terminated. Exit from Power-down can be initiated either
by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not
change the on-chip RAM. The reset should not be activated before V
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.
Figure
18-1. Either a quartz crystal or
Figure
CC
is restored to its normal
18-2. There are no
1921D–MICRO–6/08