PIC16C774-E/PQ Microchip Technology, PIC16C774-E/PQ Datasheet - Page 58
![IC MCU OTP 4KX14 A/D PWM 44-MQFP](/photos/6/59/65984/150-44-pqfp_sml.jpg)
PIC16C774-E/PQ
Manufacturer Part Number
PIC16C774-E/PQ
Description
IC MCU OTP 4KX14 A/D PWM 44-MQFP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C773SO.pdf
(201 pages)
3.PIC16C774P.pdf
(13 pages)
4.PIC16C774P.pdf
(16 pages)
Specifications of PIC16C774-E/PQ
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-MQFP, 44-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16C774E/PQ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C774-E/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C773SO PDF datasheet #2
- PIC16C774P PDF datasheet #3
- PIC16C774P PDF datasheet #4
- Current page: 58 of 201
- Download datasheet (3Mb)
PIC16C77X
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur.
SSPBUF (SSPSR) for data transmission.
EXAMPLE 8-1:
LOOP BTFSS SSPSTAT, BF
The SSPSR is not directly readable or writable, and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP status register (SSPSTAT) indi-
cates the various status conditions.
8.1.2
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
isters, and then set bit SSPEN. This configures the
FIGURE 8-5:
DS30275A-page 58
BSF
GOTO
BCF
MOVF
MOVWF RXDATA
MOVF
MOVWF SSPBUF
ENABLING SPI I/O
Example 8-1
STATUS, RP0
LOOP
STATUS, RP0
SSPBUF, W
TXDATA, W
SPI Master SSPM3:SSPM0 = 00xxb
SPI MASTER/SLAVE CONNECTION
LOADING THE SSPBUF
(SSPSR) REGISTER
MSb
PROCESSOR 1
Serial Input Buffer
shows the loading of the
Shift Register
(SSPBUF)
(SSPSR)
;Specify Bank 1
;Has data been
;received
;(transmit
;complete)?
;No
;Specify Bank 0
;W reg = contents
;of SSPBUF
;Save in user RAM
;W reg = contents
; of TXDATA
;New data to xmit
LSb
Advance Information
SDO
SCK
SDI
Serial Clock
SDI, SDO, SCK, and SS pins as serial port pins. For the
pins to behave as the serial port function, some must
have their data direction bits (in the TRIS register)
appropriately programmed. That is:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
8.1.3
Figure 8-5
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite edge
of the clock. Both processors should be programmed to
same Clock Polarity (CKP), then both controllers would
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
cleared
SDO
SCK
SDI
TYPICAL CONNECTION
shows a typical connection between two
SPI Slave SSPM3:SSPM0 = 010xb
MSb
Serial Input Buffer
Shift Register
PROCESSOR 2
(SSPBUF)
(SSPSR)
1999 Microchip Technology Inc.
LSb
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