PIC16F874-04E/L Microchip Technology, PIC16F874-04E/L Datasheet - Page 77
![IC MCU FLASH 4KX14 EE 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC16F874-04E/L
Manufacturer Part Number
PIC16F874-04E/L
Description
IC MCU FLASH 4KX14 EE 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F873-04SO.pdf
(218 pages)
4.PIC16F873-04SO.pdf
(5 pages)
5.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F874-04E/L
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-PLCC
For Use With
309-1040 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1039 - ADAPTER 44-PLCC TO 40-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16F87404E/L
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F874-04E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F873-04SO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- Current page: 77 of 218
- Download datasheet (4Mb)
TABLE 9-2:
9.2.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then,
the SCL pin should be enabled by setting bit CKP
(SSPCON<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA sig-
nal is valid during the SCL high time (Figure 9-7).
FIGURE 9-6:
SDA
SCL
SSPIF
Note:
BF (SSPSTAT<0>)
2001 Microchip Technology Inc.
SSPOV (SSPCON<6>)
Transfer is Received
Status Bits as Data
BF
0
1
1
0
S
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
A7 A6 A5 A4 A3 A2 A1
1
Slave Transmission
SSPOV
2
Receiving Address
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
3
I
2
4
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
5
6
SSPSR
7
8
R/W=0
ACK
9
Yes
Yes
No
No
D7
SSPBUF
1
D6
2
Cleared in software
SSPBUF register is read
Receiving Data
D5
3
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line is high (not ACK), then the
data transfer is complete. When the not ACK is latched
by the slave, the slave logic is reset and the slave then
monitors for another occurrence of the START bit. If the
SDA line was low (ACK), the transmit data must be
loaded into the SSPBUF register, which also loads the
SSPSR register. Then the SCL pin should be enabled
by setting the CKP bit.
Generate ACK
D1
7
Pulse
D0
8
Yes
No
No
No
ACK
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
ACK is not sent.
PIC16F87X
(SSP Interrupt occurs
D3
5
D2
6
Set bit SSPIF
if enabled)
D1
7
Yes
Yes
Yes
Yes
D0
DS30292C-page 75
8
ACK
Not
9
Bus Master
Terminates
Transfer
P
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