PIC16LC63A-04I/ML Microchip Technology, PIC16LC63A-04I/ML Datasheet - Page 56
![IC MCU OTP 4KX14 PWM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LC63A-04I/ML
Manufacturer Part Number
PIC16LC63A-04I/ML
Description
IC MCU OTP 4KX14 PWM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Specifications of PIC16LC63A-04I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
PIC16LC63A04I/ML
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PIC16C63A/65B/73B/74B
REGISTER 10-1:
DS30605C-page 56
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
bit 7
SMP: SPI Data Input Sample Phase
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I
This bit must be maintained clear
CKE: SPI Clock Edge Select (see Figure 10-2, Figure 10-3, and Figure 10-4)
SPI mode:
CKP = 0:
1 = Data transmitted on rising edge of SCK (Microwire alternate)
0 = Data transmitted on falling edge of SCK
CKP = 1:
1 = Data transmitted on falling edge of SCK (Microwire default)
0 = Data transmitted on rising edge of SCK
I
This bit must be maintained clear
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: STOP bit (I
START bit is detected last. SSPEN is cleared.
1 = Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0 = STOP bit was not detected last
S: START bit (I
the STOP bit is detected last. SSPEN is cleared.
1 = Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0 = START bit was not detected last
R/W: Read/Write bit information (I
ing the last address match. This bit is only valid from the address match to the next START bit,
STOP bit, or ACK bit.
1 = Read
0 = Write
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
Legend:
R = Readable bit
-n = Value at POR
2
2
C mode:
C mode:
R/W-0
SMP
2
C mode only):
2
R/W-0
C mode only). This bit is cleared when the SSP module is disabled, or when the
CKE
2
C mode only). This bit is cleared when the SSP module is disabled, or when
2
C modes):
2
C mode only)
R-0
D/A
W = Writable bit
’1’ = Bit is set
2
C mode only)
2
C mode only). This bit holds the R/W bit information follow-
R-0
P
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R-0
S
®
R/W
R-0
)
2000 Microchip Technology Inc.
x = Bit is unknown
R-0
UA
R-0
BF
bit 0
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