PIC16F877T-10E/PQ Microchip Technology, PIC16F877T-10E/PQ Datasheet - Page 86
![IC MCU FLASH 8KX14 EE 44-MQFP](/photos/6/59/65984/150-44-pqfp_sml.jpg)
PIC16F877T-10E/PQ
Manufacturer Part Number
PIC16F877T-10E/PQ
Description
IC MCU FLASH 8KX14 EE 44-MQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873-04SO.pdf
(218 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F877T-10E/PQ
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-MQFP, 44-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16F877T10E/PQ
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F877T-10E/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- PIC16F873-04SO PDF datasheet #6
- Current page: 86 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
5.2
5.3
5.4
DS31005A-page 5-4
General Instruction Format
Central Processing Unit (CPU)
Instruction Clock
The Mid-Range MCU instructions can be broken down into four general formats as shown in
Figure
opcode size is what allows 35 instructions to be implemented.
Figure 5-1: General Format for Instructions
The CPU can be thought of as the “brains” of the device. It is responsible for fetching the correct
instruction for execution, decoding that instruction, and then executing that instruction.
The CPU sometimes works in conjunction with the ALU to complete the execution of the instruc-
tion (in arithmetic and logical operations).
The CPU controls the program memory address bus, the data memory address bus, and
accesses to the stack.
Each instruction cycle (T
as the device oscillator cycle time (T
Decode, Read, Process Data, Write, etc., of each instruction cycle. The following diagram shows
the relationship of the Q cycles to the instruction cycle.
The four Q cycles that make up an instruction cycle (T
Each instruction will show a detailed Q cycle operation for the instruction.
Figure 5-2: Q Cycle Activity
Bit-oriented file register operations
Byte-oriented file register operations
Literal and control operations
General
CALL and GOTO instructions only
Q1:
Q2:
Q3:
Q4:
13
13
13
13
5-1. As can be seen the opcode for the instruction varies from 3-bits to 6-bits. This variable
Tosc
OPCODE
OPCODE
OPCODE
OPCODE
Instruction Decode Cycle or forced No operation
Instruction Read Data Cycle or No operation
Process the Data
Instruction Write Data Cycle or No operation
11
Q1
10 9
10
8
Q2
CY
b (BIT #)
d
T
7
) is comprised of four Q cycles (Q1-Q4). The Q cycle time is the same
8
CY
Q3
1
6
7
7 6
k (literal)
Q4
f (FILE #)
k (literal)
OSC
f (FILE #)
Q1
). The Q cycles provide the timing/designation for the
Q2
0
0
0
0
T
CY
Q3
2
CY
) can be generalized as:
Q4
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
b = 3-bit bit address
f = 7-bit file register address
k = 8-bit immediate value
k = 11-bit immediate value
Q1
1997 Microchip Technology Inc.
Q2
T
CY
Q3
3
Q4
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