PIC16F84AT-04E/SS Microchip Technology, PIC16F84AT-04E/SS Datasheet - Page 22
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PIC16F84AT-04E/SS
Manufacturer Part Number
PIC16F84AT-04E/SS
Description
IC MCU CMOS 4MHZ 1K FLASH 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16F84A-04P.pdf
(88 pages)
3.PIC16F84A-04P.pdf
(6 pages)
Specifications of PIC16F84AT-04E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
PIC16F84A
5.2.1
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on the fly” during program
execution).
FIGURE 5-2:
TABLE 5-1:
DS35007B-page 20
01h
0Bh,8Bh
81h
85h
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
Address
Note:
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
WDT Enable bit
RA4/T0CKI
Watchdog
CLKOUT (= F
Timer
pin
To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro™ Mid-Range Reference Man-
ual, DS33023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
SWITCHING PRESCALER
ASSIGNMENT
TMR0
INTCON
OPTION_REG
TRISA
Name
REGISTERS ASSOCIATED WITH TIMER0
OSC
T0SE
/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
0
1
Timer0 Module Register
RBPU INTEDG
Bit 7
GIE
PSA
—
M
U
X
0
1
EEIE
Bit 6
T0CS
—
M
U
X
T0CS
Bit 5
T0IE
8-bit Prescaler
8 - to - 1 MUX
0
—
Time-out
8
M U X
WDT
PORTA Data Direction Register
T0SE
INTE
Bit 4
1
0
1
PSA
M
U
X
RBIE
Bit 3
PSA
5.3
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module Interrupt Ser-
vice Routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut-off during SLEEP.
PSA
Bit 2
T0IF
PS2
PS2:PS0
Timer0 Interrupt
Cycles
SYNC
2
Bit 1
INTF
PS1
RBIF
Bit 0
PS0
2001 Microchip Technology Inc.
TMR0 reg
Data Bus
xxxx xxxx
0000 000x
1111 1111
---1 1111
Value on
POR,
BOR
8
Set Flag bit T0IF
on Overflow
Value on all
uuuu uuuu
0000 000u
1111 1111
---1 1111
RESETS
other