PIC16F84AT-20E/SS Microchip Technology, PIC16F84AT-20E/SS Datasheet - Page 329
![IC MCU CMOS 20MHZ 1K FLSH 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F84AT-20E/SS
Manufacturer Part Number
PIC16F84AT-20E/SS
Description
IC MCU CMOS 20MHZ 1K FLSH 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC16F84A-04P.pdf
(88 pages)
3.PIC16F84A-04P.pdf
(6 pages)
Specifications of PIC16F84AT-20E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
POR, WDT
Number Of I /o
13
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
68 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
For Use With
XLT20SS1-1 - SOCKET TRANSITION 20DIP 20SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
- Current page: 329 of 688
- Download datasheet (3Mb)
17.4.18.2 Bus Collision During a Repeated Start Condition
1997 Microchip Technology Inc.
SDA
SCL
RSEN
BCLIF
S
SSPIF
During a Repeated Start condition, a bus collision occurs if:
a)
b)
When the user de-asserts SDA and the pin is allowed to float high, the BRG is loaded with
SSPADD<6:0>, and counts down to zero. The SCL pin is then de-asserted, and when sampled
high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e. another master,
Figure
is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus
collision occurs, because no two masters can assert SDA at exactly the same time.
If, however, SCL goes from high to low before the BRG times out and SDA has not already been
asserted, then a bus collision occurs. In this case, another master is attempting to transmit a data
’1’ during the Repeated Start condition,
If at the end of the BRG time out both SCL and SDA are still high, the SDA pin is driven low, the
BRG is reloaded, and begins counting. At the end of the count, regardless of the status of the
SCL pin, the SCL pin is driven low and the Repeated Start condition is complete.
Figure 17-38: Bus Collision During a Repeated Start Condition (Case 1)
A low level is sampled on SDA when SCL goes from low level to high level.
SCL goes low before SDA is asserted low, indicating that another master is attempting to
transmit a data ’1’.
17-38, is attempting to transmit a data ’0’). If, however, SDA is sampled high then the BRG
Preliminary
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL
Figure
17-39.
Section 17. MSSP
Cleared in software
'0'
'0'
DS31017A-page 17-53
17
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