PIC17C752T-33E/L Microchip Technology, PIC17C752T-33E/L Datasheet - Page 64
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PIC17C752T-33E/L
Manufacturer Part Number
PIC17C752T-33E/L
Description
IC MCU CMOS 33MHZ 8K EPRM 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C752T-33E/L
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
16KB (8K x 16)
Program Memory Type
OTP
Ram Size
454 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C752T-33E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- Current page: 64 of 304
- Download datasheet (6Mb)
PIC17C7XX
8.3
The table read allows the program memory to be read.
This allows constants to be stored in the program mem-
ory space and retrieved into data memory when
needed. Example 8-2 reads the 16-bit value at program
memory address TBLPTR. After the dummy byte has
been read from the TABLATH, the TABLATH is loaded
with the 16-bit data from program memory address
TBLPTR and then increments the TBLPTR value. The
first read loads the data into the latch and can be con-
sidered a dummy read (unknown data loaded into ’f’).
INDF0 should be configured for either auto-increment
or auto-decrement.
FIGURE 8-7:
FIGURE 8-8:
DS30289B-page 64
AD15:AD0
Instruction
Instruction
Executed
Fetched
Table Reads
ALE
WR
OE
AD15:AD0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
’1’
Instruction
Instruction
Executed
INST (PC-1)
Fetched
TABLRD1
PC
TABLRD TIMING
TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)
ALE
WR
OE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
’1’
TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1 TABLRD2 cycle2
INST (PC-1)
TABLRD
TABLRD2
PC
PC+1
TABLRD cycle1
Data read cycle
INST (PC+1)
PC+1
TBL1 Data in 1
EXAMPLE 8-2:
MOVLW
MOVWF
MOVLW
MOVWF
TABLRD
TLRD
TABLRD
INST (PC+2)
Data read cycle
TABLRD cycle2
PC+2
TBL
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
0, 1, DUMMY
1, INDF0
0, 1, INDF0
Data in
Data read cycle
TABLE READ
TBL2
INST (PC+2)
INST (PC+1)
2000 Microchip Technology Inc.
PC+2
; Dummy read,
;
;
; Read HI byte
;
; Read LO byte
;
;
;
Data in 2
;
;
;
Updates TABLATH
Increments TBLPTR
of TABLATH
of TABLATL and
Update TABLATH
Increment TBLPTR
INST (PC+3)
address
INST (PC+2)
PC+3
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