PIC16LF87T-I/ML Microchip Technology, PIC16LF87T-I/ML Datasheet - Page 134
![IC MCU FLASH 4KX14 EEPROM 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16LF87T-I/ML
Manufacturer Part Number
PIC16LF87T-I/ML
Description
IC MCU FLASH 4KX14 EEPROM 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16LF627A-IP.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16F87-IP.pdf
(228 pages)
4.PIC16F87-IP.pdf
(8 pages)
5.PIC16F87-IP.pdf
(4 pages)
6.PIC16F87-IP.pdf
(8 pages)
Specifications of PIC16LF87T-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC16LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
SSP, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- PIC16LF627A-IP PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC16F87-IP PDF datasheet #3
- PIC16F87-IP PDF datasheet #4
- PIC16F87-IP PDF datasheet #5
- PIC16F87-IP PDF datasheet #6
- Current page: 134 of 228
- Download datasheet (5Mb)
PIC16F87/88
15.2
The PIC16F87/88 differentiates between various kinds
of Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• WDT Reset during normal operation
• WDT wake-up during Sleep
• Brown-out Reset (BOR)
FIGURE 15-1:
DS30487C-page 132
OSC1
MCLR
V
DD
Reset
31.25 kHz
INTRC
OST/PWRT
Brown-out
V
Module
Detect
DD
WDT
Reset
Rise
OST
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
PWRT
10-bit Ripple Counter
Time-out
Reset
WDT
11-bit Ripple Counter
BOREN
Power-on Reset
External
Reset
Sleep
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brown-
out Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared
differently in different Reset situations, as indicated in
Table 15-3. These bits are used in software to deter-
mine the nature of the Reset. Upon a POR, BOR or
wake-up from Sleep, the CPU requires approximately
5-10 s to become ready for code execution. This
delay runs in parallel with any other timers. See
Table 15-4 for a full description of Reset states of all
registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 15-1.
2005 Microchip Technology Inc.
S
R
Q
Chip_Reset
Enable PWRT
Enable OST
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