PIC18LF2539T-I/SO Microchip Technology, PIC18LF2539T-I/SO Datasheet - Page 73

• Manufacturer Part Number: PIC18LF2539T-I/SO
• Description: IC MCU FLASH 12KX16 EE AD 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF2539T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 24KB (12K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1408 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1408 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1
The INTCON Registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 8-1:
 2002 Microchip Technology Inc.
INTCON Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON REGISTER
GIE/GIEH: Global Interrupt Enable bit
1 = Enables all high priority interrupts
0 = Disables all interrupts
PEIE/GIEL: Peripheral Interrupt Enable bit
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
INT0IE
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
RBIF
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
bit 7
Legend:
R = Readable bit
- n = Value at POR
GIE/GIEH
Note 1: Maintain this bit cleared (= 0).
R/W-0
(2)
(1)
: RB Port Change Interrupt Flag bit
2: A mismatch condition will continue to set this bit. Reading PORTB will end the
: INT0 External Interrupt Enable bit
mismatch condition and allow the bit to be cleared.
PEIE/GIEL
R/W-0
Preliminary
TMR0IE
R/W-0
W = Writable bit
‘1’ = Bit is set
INT0IE
R/W-0
Note:
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
R/W-0
RBIE
PIC18FXX39
TMR0IF
R/W-0
x = Bit is unknown
INT0IF
R/W-0
DS30485A-page 71
RBIF
R/W-x
bit 0
(2)