PIC18LF8621T-I/PT Microchip Technology, PIC18LF8621T-I/PT Datasheet - Page 273
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PIC18LF8621T-I/PT
Manufacturer Part Number
PIC18LF8621T-I/PT
Description
IC PIC MCU FLASH 32KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F6525-IPT.pdf
(396 pages)
Specifications of PIC18LF8621T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Number Of Timers
2 x 8 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF8621T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 24-3:
24.4.1
The user memory may be read to or written from any
location using the table read and table write instruc-
tions. The Device ID register may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In user mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from table writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the
EBTRn bit set to ‘0’, a table read instruction that
executes from within that block is allowed to read. A
2005 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
Note 1:
File Name
Unimplemented in PIC18FX525 devices.
PROGRAM MEMORY
CODE PROTECTION
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
SUMMARY OF REGISTERS ASSOCIATED WITH CODE PROTECTION
WRTD
Bit 7
CPD
—
—
—
—
EBTRB
WRTB
Bit 6
CPB
—
—
—
PIC18F6525/6621/8525/8621
WRTC
Bit 5
—
—
—
—
—
table read instruction that executes from a location out-
side of that block is not allowed to read and will result
in reading ‘0’s. Figures 24-4 through 24-6 illustrate
table write and table read protection.
Bit 4
—
—
—
—
—
—
Note:
EBTR3
WRT3
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
CP3
Bit 3
—
—
—
(1)
(1)
(1)
EBTR2
WRT2
Bit 2
CP2
—
—
—
EBTR1
WRT1
Bit 1
CP1
DS39612B-page 271
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—
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