AT89LV55-12PC Atmel, AT89LV55-12PC Datasheet
AT89LV55-12PC
Specifications of AT89LV55-12PC
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AT89LV55-12PC Summary of contents
Page 1
... RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89LV55 is designed with static logic for operation down to zero fre- quency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys- tem to continue functioning ...
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... Pin Configurations 2.1 44A – 44-lead TQFP 2.2 40P6 – 40-lead PDIP 2.3 44J – 44-lead PLCC AT89LV55 2 0811E–MICRO–9/08 ...
Page 3
... PORT 0 DRIVERS PORT 0 PORT 2 RAM LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PORT 1 LATCH PORT 1 DRIVERS P1.0 - P1.7 AT89LV55 P2.0 - P2.7 PORT 2 DRIVERS FLASH LATCH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM COUNTER DPTR PORT 3 ...
Page 4
... Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program- ming and verification. AT89LV55 4 ) because of the internal pullups. IL Alternate Functions ...
Page 5
... TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter- nal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I Port 3 also serves the functions of various special features of the AT89LV55, as shown in the following table. Port Pin P3 ...
Page 6
... XTAL2 Output from the inverting oscillator amplifier. 5. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1. Table 5-1. AT89LV55 SFR Map and Reset Values 0F8H B 0F0H 00000000 0E8H ACC 0E0H 00000000 ...
Page 7
... Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. 0811E–MICRO–9/08 Table 8-2) for Timer 2. The register pair (RCAP2H, RCAP2L) are the RCLK TCLK EXEN2 AT89LV55 Reset Value = 0000 0000B TR2 C/T2 CP/RL2 Table 5- 7 ...
Page 8
... Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space. 7. Timer 0 and 1 Timer 0 and Timer 1 in the AT89LV55 operate the same way as Timer 0 and Timer 1 in the AT89C51. For further information on the timers’ operation, please click on the document link below: http://www ...
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... X X Figure 8-1. Timer 2 in Capture Mode Table 8-2). Upon reset, the DCEN bit is set that timer 2 will default to count shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options AT89LV55 TR2 MODE 1 16-bit Auto-reload 1 16-bit Capture 1 Baud Rate Generator ...
Page 10
... Not Bit Addressable – – Bit 7 6 Symbol Function – Not implemented, reserved for future use. T20E Timer 2 Output Enable bit. DCEN When set, this bit allows Timer configured as an up/down counter. AT89LV55 10 – – – Reset Value = XXXX XX00B – T20E DCEN 0811E– ...
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... Figure 8-3. Timer 2 Auto Reload Mode (DCEN = 1) Figure 8-4. Timer 2 in Baud Rate Generator Mode 0811E–MICRO–9/08 AT89LV55 11 ...
Page 12
... The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. AT89LV55 12 Timer 2 Overflow Rate Modes 1 and 3 Baud Rates ...
Page 13
... RCAP2H and RCAP2L. 11. UART The UART in the AT89LV55 operates the same way as the UART in the AT89C51. For further information on the UART operation, please click on the document link below: http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF 0811E– ...
Page 14
... Interrupts The AT89LV55 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE ...
Page 15
... To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory. 0811E–MICRO–9/08 AT89LV55 Figure 15-1. Either a quartz crystal or Figure 15-2 ...
Page 16
... Status of External Pins During Idle and Power-down Modes Mode Program Memory Idle Internal Idle External Power-down Internal Power-down External AT89LV55 16 is restored to its normal operating level and must be held active long CC C1 ± for Crystals = 40 pF ± for Ceramic Resonators ALE PSEN ...
Page 17
... Program Memory Lock Bits The AT89LV55 has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in Table 16- When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated ...
Page 18
... P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows: (030H) = 1EH indicates manufactured by Atmel (031H) = 65H indicates 89LV55 (032H) = FFH indicates 12V programming AT89LV55 18 AT89LV55 ADDR. P1.0 - P1.7 0000H/4FFFH P2 A13 P3 ...
Page 19
... ADDR. 0000H/4FFFH A8 - A13 A14* SEE FLASH PROGRAMMING MODES TABLE 3-12 MHz RST PSEN ALE/PROG AT89LV55 +5V AT89LV55 V P1.0 - P1.7 CC PGM DATA P0 P2.0 - P2.5 (USE 10K PULLUPS) P3.0 P2.6 ALE P2.7 P3 P3.7 XTAL2 EA V XTAL1 RST I H GND PSEN EA/V P2.6 P2.7 PP 12V ...
Page 20
... Address to Data Valid AVQV t ENABLE Low to Data Valid ELQV t Data Float After ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC 20. Flash Programming and Verification Waveforms (V AT89LV55 20 PP Min Max 11.5 12.5 1 48t CLCL 48t CLCL 48t CLCL ...
Page 21
... OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT89LV55 Stresses beyond those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional oper- ...
Page 22
... ALE Low Low LLWL t Address Low AVWL t Data Valid to WR Transition QVWX t Data Valid to WR High QVWH t Data Hold After WR WHQX t RD Low to Address Float RLAZ High to ALE High WHLH AT89LV55 22 12 MHz Oscillator Variable Oscillator Min Max Min 0 127 CLCL CLCL CLCL ...
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... External Program Memory Read Cycle 25. External Data Memory Read Cycle 0811E–MICRO–9/08 AT89LV55 23 ...
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... External Data Memory Write Cycle 27. External Clock Drive Waveforms AT89LV55 24 0811E–MICRO–9/08 ...
Page 25
... Edge Clock Rising Edge to Input Data t XHDV Valid 0811E–MICRO–9/08 Min 0 83 5.0V ± 20% and Load Capacitance = 80 pF MHz Osc Min Max 1.0 700 50 0 700 AT89LV55 Max Units 12 MHz Variable Oscillator Min Max 12t CLCL 10t - 133 CLCL 2t - 117 ...
Page 26
... Float Waveforms Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V AT89LV55 26 (1) /V level occurs 0811E– ...
Page 27
... Notes: 0811E–MICRO–9/08 1. XTAL1 tied to GND for I (power-down Lock bits programmed AT89LV55 27 ...
Page 28
... Ordering Information Speed Power (MHz) Supply Ordering Code AT89LV55-12AC AT89LV55-12JC AT89LV55-12PC 12 2.7V - 6.0V AT89LV55-12AI AT89LV55-12JI AT89LV55-12PI 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) ...
Page 29
... Orchard Parkway San Jose, CA 95131 R 0811E–MICRO–9/08 B PIN 1 IDENTIFIER TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) AT89LV55 A2 A COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM SYMBOL A – – A1 0.05 – ...
Page 30
... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89LV55 30 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...
Page 31
... A1 0.381 – D 52.070 – E 15.240 – E1 13.462 – B 0.356 – B1 1.041 – L 3.048 – C 0.203 – eB 15.494 – e 2.540 TYP DRAWING NO. AT89LV55 MAX NOTE 4.826 – 52.578 Note 2 15.875 13.970 Note 2 0.559 1.651 3.556 0.381 17.526 09/28/01 REV. 40P6 B 31 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...