DSPIC30F6010T-20I/PF Microchip Technology, DSPIC30F6010T-20I/PF Datasheet - Page 5

• Manufacturer Part Number: DSPIC30F6010T-20I/PF
• Description: IC PSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010T-20I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6010T20IP

8. Module: 32-bit General Purpose Timers
9. Module: 12-bit 100 Ksps A/D Converter
 2004 Microchip Technology Inc.
Pairs of 16-bit timers may be combined to form
32-bit timers. For example, Timer2 and Timer3 are
combined into a single 32-bit timer. For this
release of silicon, when a 32-bit timer is prescaled
by ratios other than 1:1, unexpected results may
occur.
Work around
None. The application may only use the 1:1
prescaler for 32-bit timers.
Input Channel Scanning allows the A/D converter
to acquire and convert signals on a selected set of
“MUX A” input pins in sequence. This function is
controlled by the CSCNA (ADCON2<11>) bit and
the ADCSSL SFR.
The ALTS (ADCON2<0>) bit, when set, allows the
A/D converter to alternately acquire and convert a
“MUX A” input signal and a “MUX B” input signal in
an interleaved fashion.
When both CSCNA and ALTS are set, the A/D
module should scan MUX A input pins while
alternating with a fixed MUX B input pin. However,
for this release of silicon, when both features are
enabled simultaneously, the last input pin enabled
for channel scanning in the ADCSSL SFR, is not
scanned. Thus, the A/D converter converts one
channel less than the number specified in the scan
sequence. Note that this erratum does not affect
devices that have a 10-bit 500 Ksps A/D converter.
Work around
The user may enable an extra (“dummy”) input pin
in the channel-scanning sequence. For example, if
it is desirable to scan pins AN3, AN4 and AN5 on
the set of MUX A inputs while interleaving conver-
sion from AN6 on the MUX B input, the user may
configure the A/D converter as follows:
For the configuration above, AN15 is the dummy
input that will not be scanned. On the A/D interrupt,
the A/D buffer will contain conversions from the
following pins in sequence:
- ADCON2 = 0x041D
- ADCHS = 0x0600
- ADCSSL = 0x8038
- ADCBUF0 = AN3
- ADCBUF1 = AN6
- ADCBUF2 = AN4
- ADCBUF3 = AN6
- ADCBUF4 = AN5
- ADCBUF5 = AN6
- ADCBUF6 = AN3
- ADCBUF7 = AN6
Advance Information
10. Module: 10-bit A/D Converter –
11. Module: Data Converter Interface – Slave
Sampling multiple channels sequentially using any
conversion trigger source other than the auto-
convert feature requires SAMC bits to be non-
zero. Thus, if the following conditions are all
satisfied, the module may not operate as specified:
- Multiple S/H channels are sampled
- Auto-convert option is not chosen as the
- SAMC(ADCON3<12:8>) is equal to ‘00000’
Work around
Set the value of the SAMC bits to anything other
than ‘00000’. The module will now operate as
specified.
The Data Converter Interface (DCI) module does
not function correctly in Slave mode when the
following conditions are true:
• The DCI module is configured to transmit/
• The frame length chosen is longer than 1 word,
Work around
The following work around may be applied to
enable DCI communication in Slave mode when it
is configured to transmit one serial clock after the
frame synchronization pulse is received in a
multi-word frame:
1. Set the DJST bit to ‘1’.
2. Enable an additional time slot immediately
3. Enable an additional transmit/receive buffer
4. Shift the data word by 1 bit to the right and load
receive one serial clock (bit clock) after the
frame synchronization pulse,
DJST(DCICON1<5>) = 0.
COFSG(DCICON2<8:5>) > 0000.
sequentially
CHPS(ADCON2<9:8>) is not equal to ‘00’ and
SIMSAM(ADCON1<3>) = 0
conversion trigger
SSRC(ADCON1<7:5>) is not equal to ‘111’
following
communication.
word (modify COFSG bits) or an additional bit
per word (modify WS) for each time slot
intended for communication.
the transmit buffer word(s), such that the LS Bit
of the original data word to be transmitted is
loaded into the additionally enabled bit of the
transmit buffer register, TXBUFn, or the MS bit
of the additionally enabled transmit buffer,
TXBUFn+1.
Sequential Samping
Mode
dsPIC30F601X
each
time
slot
DS80176E-page 5
intended
for