DSPIC30F6010T-20I/PF Microchip Technology, DSPIC30F6010T-20I/PF Datasheet - Page 5

• Manufacturer Part Number: DSPIC30F6010T-20I/PF
• Description: IC PSPIC MCU/DSP 144K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6010T-20I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• For Use With: DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6010T20IP

8. Module: Interrupt Controller
EXAMPLE 8:
EXAMPLE 9:
 2004 Microchip Technology Inc.
mov
mov
disi #2
mov
mov
asm volatile(
//Note: There are no commas between
//
//
A specific write sequence for IPC2 (Interrupt
Priority Control 2) SFR is required to prevent
possible data corruption in the IEC2 (Interrupt
Enable Control 2) SFR. Interrupts must be
disabled during this IPC2 SFR write sequence.
Work around
An example of this write sequence is shown in
Example 8.
When coding in C, the write sequence shown
above can be implemented using inline assembly
instructions. The equivalent write sequence using
the C30 compiler is shown in Example 9.
#IPC2, w0
#0x4444, w1
w1, IPC2
#IPC2, w0
the quoted strings in the code
segment above.
“mov.d w0, [w15++]\n\t”
“mov
“mov
“disi
“mov
“mov
“mov.d [--w15], w0”);
;Point w0 to IPC2
;Write data to go to IPC2
;Disable interrupts for
;next two cycles
;Write the data to IPC2
;Target w1 to keep IPC2
;address on bus
#IPC2,w0\n\t”
#0x4444,w1\n\t”
w1, IPC2\n\t”
#IPC2, w0\n\t”
#2\n\t”
Advance Information
9. Module: Interrupt Controller – Traps
EXAMPLE 10:
.global
__MathError:
Catastrophic Accumulator Overflow Traps are
enabled as follows:
A carry generated out of bit 39 in the accumulator
causes a catastrophic overflow of the accumulator
since the sign-bit has been destroyed. If a Math
Error trap handler has been defined, the processor
will vector to the Math Error trap handler upon a
catastrophic overflow.
If the respective accumulator overflow status bit,
OA or OB (SR<15/14>), is not cleared within the
trap handler routine prior to exiting the trap handler
routine, the processor will immediately re-enter the
trap handler routine.
Work around
If a Math Error Trap occurs due to a catastrophic
accumulator overflow, the overflow status flags,
OA and/or OB (SR<15/14>), should be cleared
within the trap handler routine. Subsequently, the
MATHERR (INTCON1<4>) flag bit should be
cleared within the trap handler prior to executing
the RETFIE instruction.
Since the OA and OB bits are read-only bits, it will
be necessary to execute a dummy accumulator-
based instruction within the trap service routine in
order to clear these status bits and eventually clear
the MATHERR trap flag. This is shown in
Example 10.
- COVTE (INTCON1<8>) = 1
- SATA/SATB (CORCON <7/6>) = 0
__MathError
dsPIC30F6010
BTSC
CLR
BTSC
CLR
BCLR
RETFIE
SR, #OA
A
SR, #OB
B
INTCON1, #MATHERR
DS80182E-page 5