PIC12F635-E/MF Microchip Technology, PIC12F635-E/MF Datasheet - Page 65
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PIC12F635-E/MF
Manufacturer Part Number
PIC12F635-E/MF
Description
IC MCU FLASH 1KX14 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Specifications of PIC12F635-E/MF
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-DFN
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFNAC162057 - MPLAB ICD 2 HEADER 14DIPXLT08DFN - SOCKET TRANSITION ICE 8DFNAC164032 - ADAPTER PICSTART PLUS 8DFN/DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
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REGISTER 5-1:
TABLE 5-1:
© 2007 Microchip Technology Inc.
TMR0
INTCON
OPTION_REG
TRISA
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
R/W-1
RAPU
Name
Timer0 module.
A dedicated 16-bit WDT postscaler is available. See Section 12.11 “Watchdog Timer (WDT)” for more
information.
RAPU: PORTA Pull-up Enable bit
1 = PORTA pull-ups are disabled
0 = PORTA pull-ups are enabled by individual PORT latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (F
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Timer0 Module Register
RAPU INTEDG
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7
INTEDG
GIE
R/W-1
—
OPTION_REG: OPTION REGISTER
BIT VALUE
PEIE
Bit 6
000
001
010
011
100
101
110
111
—
W = Writable bit
‘1’ = Bit is set
R/W-1
T0CS
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
T0CS
Bit 5
TMR0 RATE
T0IE
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
T0SE
INTE
Bit 4
R/W-1
T0SE
PIC12F635/PIC16F636/639
WDT RATE
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
OSC
RAIE
Bit 3
PSA
/4)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
PSA
Bit 2
T0IF
PS2
INTF
Bit 1
PS1
R/W-1
PS2
RAIF
Bit 0
PS0
x = Bit is unknown
xxxx xxxx uuuu uuuu
0000 000x 0000 000x
1111 1111 1111 1111
POR, BOR
Value on:
R/W-1
PS1
DS41232D-page 63
Value on
all other
Resets
R/W-1
PS0
bit 0
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