PIC16F639-E/P Microchip Technology, PIC16F639-E/P Datasheet - Page 19
PIC16F639-E/P
Manufacturer Part Number
PIC16F639-E/P
Description
IC MCU FLASH 2KX14 20DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC12F635-ISN.pdf
(234 pages)
3.PIC16F636-ISL.pdf
(8 pages)
4.PIC16F636-ISL.pdf
(4 pages)
5.PIC16F639-ISS.pdf
(6 pages)
Specifications of PIC16F639-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LVD, POR, WDT
Number Of I /o
11
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-DIP (0.300", 7.62mm)
For Use With
AC162066 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOICDM163029 - BOARD PICDEM FOR MECHATRONICSACICE0203 - MPLABICE 20P 300 MIL ADAPTER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
- PIC16F616T-ISL PDF datasheet
- PIC12F635-ISN PDF datasheet #2
- PIC16F636-ISL PDF datasheet #3
- PIC16F636-ISL PDF datasheet #4
- PIC16F639-ISS PDF datasheet #5
- Current page: 19 of 234
- Download datasheet (4Mb)
2.0
2.1
The PIC12F635/PIC16F636/639 devices have a 13-bit
program counter capable of addressing an 8K x 14
program memory space. Only the first 1K x 14
(0000h-03FFh, for the PIC12F635) and 2K x 14
(0000h-07FFh, for the PIC16F636/639) is physically
implemented. Accessing a location above these
boundaries will cause a wraparound within the first
2K x 14 space. The Reset vector is at 0000h and the
interrupt vector is at 0004h (see Figure 2-1).
2.2
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose
Registers (GPR) and the Special Function Registers
(SFR). The Special Function Registers are located in
the first 32 locations of each bank. Register locations
20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs,
implemented as static RAM for the PIC16F636/639.
For the PIC12F635, register locations 40h through 7Fh
are GPRs implemented as static RAM. Register
locations F0h-FFh in Bank 1 point to addresses
70h-7Fh in Bank 0. All other RAM is unimplemented
and returns ‘0’ when read. RP0 of the STATUS register
is the bank select bit.
RP1
© 2007 Microchip Technology Inc.
0
0
1
1
RP0
MEMORY ORGANIZATION
Program Memory Organization
Data Memory Organization
0
1
0
1
Bank 0 is selected
Bank 1 is selected
Bank 2 is selected
Bank 3 is selected
PIC12F635/PIC16F636/639
FIGURE 2-1: PROGRAM MEMORY MAP AND
FIGURE 2-2: PROGRAM MEMORY MAP AND
CALL, RETURN
RETFIE, RETLW
CALL, RETURN
RETFIE, RETLW
STACK OF THE PIC12F635
STACK OF THE PIC16F636/639
On-chip Program
Access 0-7FFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Access 0-3FFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
PC<12:0>
Memory
PC<12:0>
Memory
13
13
DS41232D-page 17
0000h
0004h
0005h
07FFh
0800h
1FFFh
0000h
0004h
0005h
03FFh
0400h
1FFFh
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