AT89C5131-TISIL Atmel, AT89C5131-TISIL Datasheet - Page 103

• Manufacturer Part Number: AT89C5131-TISIL
• Description: IC 8051 MCU FLASH 32K USB 28SOIC
• Manufacturer: Atmel
• Series: AT89C513xr

Specifications of AT89C5131-TISIL

• Core Processor: C52X2
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: AT89STK-10 - KIT EVAL APPL MASS STORAGEAT89STK-05 - KIT STARTER FOR AT89C5131
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Miscellaneous States
Notes
4136B–USB–09/03
If the AA bit is reset during a transfer, SSLC will transmit the last byte of the transfer and
enter state C0h or C8h. SSLC is switched to the not addressed slave mode and will
ignore the master receiver if it continues the transfer. Thus the master receiver receives
all 1’s as serial data. While AA is reset, SSLC does not respond to its own slave
address. However, the TWI bus is still monitored and address recognition may be
resume at any time by setting AA. This means that the AA bit may be used to tempo-
rarily isolate SSLC from the TWI bus.
There are two SSCS codes that do not correspond to a define SSLC hardware state
(see Table 86). These codes are discuss hereafter.
Status F8h indicates that no relevant information is available because the serial interrupt
flag is not set yet. This occurs between other states and when SSLC is not involved in a
serial transfer.
Status 00h indicates that a bus error has occurred during an SSLC serial transfer. A bus
error is caused when a START or a STOP condition occurs at an illegal position in the
format frame. Examples of such illegal positions happen during the serial transfer of an
address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To
recover from a bus error, the STO flag must be set and SI must be cleared. This causes
SSLC to enter the not addressed slave mode and to clear the STO flag (no other bits in
SSCON are affected). The SDA and SCL lines are released and no STOP condition is
transmitted.
SSLC interfaces to the external TWI bus via two port pins: SCL (serial clock line) and
SDA (serial data line). To avoid low level asserting on these lines when SSLC is
enabled, the output latches of SDA and SLC must be set to logic 1.
CR2
0
0
0
0
1
1
1
1
CR1
0
0
1
1
0
0
1
1
CR0
0
1
0
1
0
1
0
1
F
OSCA
0.5 < . < 62.5
= 12 MHz
53.5
62.5
12.5
100
47
75
Bit Frequency (kHz)
-
F
OSCA
0.67 < . < 83
62.5
71.5
16.5
= 16 MHz
100
83
-
-
AT89C5131
(reload value range:
F
96 · (256 - reload
0-254 in mode 2)
OSCA
value Timer 1)
divided by
256
224
192
160
960
120
60
103