T89C5115-TDSIM Atmel, T89C5115-TDSIM Datasheet - Page 7
T89C5115-TDSIM
Manufacturer Part Number
T89C5115-TDSIM
Description
IC 8051 MCU FLASH 16K 24SOIC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.T89C5115-RATIM.pdf
(113 pages)
Specifications of T89C5115-TDSIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
24-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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I/O Configurations
Port Structure
4128G–8051–02/08
Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A
CPU ’write to latch’ signal initiates transfer of internal bus data into the type-D latch. A
CPU ’read latch’ signal transfers the latched Q output onto the internal bus. Similarly, a
’read pin’ signal transfers the logical level of the Port pin. Some Port data instructions
activate the ’read latch’ signal while others activate the ’read pin’ signal. Latch instruc-
tions are referred to as Read-Modify-Write instructions. Each I/O line may be
independently programmed as input or output.
Figure 1 shows the structure of Ports, which have internal pull-ups. An external source
can pull the pin low. Each Port pin can be configured either for general-purpose I/O or
for its alternate input output function.
To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-
ister (x = 1 to 4). To use a pin for general-purpose input, set the bit in the Px register.
This turns off the output FET drive.
To configure a pin for its alternate function, set the bit in the Px register. When the latch
is set, the ’alternate output function’ signal controls the output level (See Figure 1). The
operation of Ports is discussed further in ’Quasi-Bi-directional Port Operation’
paragraph.
Figure 1. Ports Structure
Note:
READ
LATCH
INTERNAL
BUS
WRITE
TO
LATCH
READ
PIN
1. The internal pull-up can be disabled on P1 when analog function is selected.
D
CL
LATCH
Q
ALTERNATE
OUTPUT
FUNCTION
ALTERNATE
INPUT
FUNCTION
VCC
INTERNAL
PULL-UP (1)
P1.x
P2.x
P3.x
P4.x
(1)
7
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