T89C51CC02CA-SISIM Atmel, T89C51CC02CA-SISIM Datasheet - Page 122
T89C51CC02CA-SISIM
Manufacturer Part Number
T89C51CC02CA-SISIM
Description
IC 8051 MCU FLASH 16K 28PLCC
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC02CA-TDSIM.pdf
(159 pages)
2.T89C51CC02CA-TDSIM.pdf
(33 pages)
3.T89C51CC02CA-TDSIM.pdf
(29 pages)
4.T89C51CC02CA-TDSIM.pdf
(148 pages)
Specifications of T89C51CC02CA-SISIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-PLCC
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC02CASISIM
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Registers
122
T89C51CC02
Table 102. ADCF Register
ADCF (S:F6h)
ADC Configuration
Reset Value = 0000 0000b
Table 103. ADCON Register
ADCON (S:F3h)
ADC Control Register
Reset Value = X000 0000b
Number
Number
CH 7
7 - 0
Bit
Bit
2-0
7
7
-
7
6
5
4
3
Mnemonic Description
Mnemonic Description
PSIDLE
PSIDLE
ADEOC
SCH2:0
ADSST
CH 0:7
ADEN
CH 6
Bit
Bit
6
6
-
Channel Configuration
Set to use P1.x as ADC input.
Clear to use P1.x as standart I/O port.
Reserved
The value read from these bits are indeterminate. Do not set these bits.
Pseudo Idle Mode (Best Precision)
Set to put in idle mode during conversion
Clear to convert without idle mode.
Enable/Standby Mode
Set to enable ADC
Clear for Standby mode.
End Of Conversion
Set by hardware when ADC result is ready to be read. This flag can generate an
interrupt.
Must be cleared by software.
Start and Status
Set to start an A/D conversion.
Cleared by hardware after completion of the conversion
Selection of Channel to Convert
See Table 101
ADEN
CH 5
5
5
ADEOC
CH 4
4
4
ADSST
CH 3
3
3
SCH2
CH 2
2
2
SCH1
CH 1
1
1
4126F–CAN–12/03
SCH0
CH 0
0
0
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